文件名称:cpu
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设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is currently executing instruction stored in the instruction register IR. Arithmetic Logic processor instructions and instructions only access memory instructions).
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下载文件列表
cpu\cpu_mem.mif
...\Quartus\ALU.bsf
...\.......\Block1.bdf
...\.......\Computer.vhd.bak
...\.......\cpu.asm.rpt
...\.......\cpu.bdf
...\.......\CPU.bsf
...\.......\cpu.done
...\.......\cpu.eda.rpt
...\.......\cpu.fit.rpt
...\.......\cpu.fit.smsg
...\.......\cpu.fit.summary
...\.......\cpu.flow.rpt
...\.......\cpu.map.rpt
...\.......\cpu.map.summary
...\.......\cpu.mif_update.rpt
...\.......\cpu.pin
...\.......\cpu.pof
...\.......\cpu.qpf
...\.......\cpu.qsf
...\.......\cpu.qws
...\.......\cpu.sdc
...\.......\cpu.sim.rpt
...\.......\cpu.sof
...\.......\cpu.sta.rpt
...\.......\cpu.sta.summary
...\.......\cpu.tan.rpt
...\.......\cpu.tan.summary
...\.......\cpu01.vwf
...\.......\cpu02.vwf
...\.......\cpu_mem.mif
...\.......\cpu_mem.mif.bak
...\.......\cpu_nativelink_simulation.rpt
...\.......\db\add_sub_9rh.tdf
...\.......\..\add_sub_jsh.tdf
...\.......\..\add_sub_lnh.tdf
...\.......\..\add_sub_lsh.tdf
...\.......\..\altsyncram_6bc1.tdf
...\.......\..\altsyncram_r1d1.tdf
...\.......\..\cpu.asm.qmsg
...\.......\..\cpu.asm.rdb
...\.......\..\cpu.cbx.xml
...\.......\..\cpu.cmp.bpm
...\.......\..\cpu.cmp.cdb
...\.......\..\cpu.cmp.ecobp
...\.......\..\cpu.cmp.hdb
...\.......\..\cpu.cmp.kpt
...\.......\..\cpu.cmp.logdb
...\.......\..\cpu.cmp.qrpt
...\.......\..\cpu.cmp.rdb
...\.......\..\cpu.cmp.tdb
...\.......\..\cpu.cmp0.ddb
...\.......\..\cpu.cmp_merge.kpt
...\.......\..\cpu.db_info
...\.......\..\cpu.eco.cdb
...\.......\..\cpu.eda.qmsg
...\.......\..\cpu.eds_overflow
...\.......\..\cpu.fit.qmsg
...\.......\..\cpu.fnsim.hdb
...\.......\..\cpu.fnsim.qmsg
...\.......\..\cpu.hier_info
...\.......\..\cpu.hif
...\.......\..\cpu.lpc.html
...\.......\..\cpu.lpc.rdb
...\.......\..\cpu.lpc.txt
...\.......\..\cpu.map.bpm
...\.......\..\cpu.map.cdb
...\.......\..\cpu.map.ecobp
...\.......\..\cpu.map.hdb
...\.......\..\cpu.map.kpt
...\.......\..\cpu.map.logdb
...\.......\..\cpu.map.qmsg
...\.......\..\cpu.map_bb.cdb
...\.......\..\cpu.map_bb.hdb
...\.......\..\cpu.map_bb.logdb
...\.......\..\cpu.mif_update.qmsg
...\.......\..\cpu.pre_map.cdb
...\.......\..\cpu.pre_map.hdb
...\.......\..\cpu.rpp.qmsg
...\.......\..\cpu.rtlv.hdb
...\.......\..\cpu.rtlv_sg.cdb
...\.......\..\cpu.rtlv_sg_swap.cdb
...\.......\..\cpu.sgate.rvd
...\.......\..\cpu.sgate_sm.rvd
...\.......\..\cpu.sgdiff.cdb
...\.......\..\cpu.sgdiff.hdb
...\.......\..\cpu.sim.cvwf
...\.......\..\cpu.sim.hdb
...\.......\..\cpu.sim.qmsg
...\.......\..\cpu.sim.rdb
...\.......\..\cpu.simfam
...\.......\..\cpu.sld_design_entry.sci
...\.......\..\cpu.sld_design_entry_dsc.sci
...\.......\..\cpu.smart_action.txt
...\.......\..\cpu.smp_dump.txt
...\.......\..\cpu.sta.qmsg
...\.......\..\cpu.sta.rdb
...\.......\..\cpu.syn_hier_info
...\.......\..\cpu.tan.qmsg
...\.......\..\cpu.taw.rdb
...\Quartus\ALU.bsf
...\.......\Block1.bdf
...\.......\Computer.vhd.bak
...\.......\cpu.asm.rpt
...\.......\cpu.bdf
...\.......\CPU.bsf
...\.......\cpu.done
...\.......\cpu.eda.rpt
...\.......\cpu.fit.rpt
...\.......\cpu.fit.smsg
...\.......\cpu.fit.summary
...\.......\cpu.flow.rpt
...\.......\cpu.map.rpt
...\.......\cpu.map.summary
...\.......\cpu.mif_update.rpt
...\.......\cpu.pin
...\.......\cpu.pof
...\.......\cpu.qpf
...\.......\cpu.qsf
...\.......\cpu.qws
...\.......\cpu.sdc
...\.......\cpu.sim.rpt
...\.......\cpu.sof
...\.......\cpu.sta.rpt
...\.......\cpu.sta.summary
...\.......\cpu.tan.rpt
...\.......\cpu.tan.summary
...\.......\cpu01.vwf
...\.......\cpu02.vwf
...\.......\cpu_mem.mif
...\.......\cpu_mem.mif.bak
...\.......\cpu_nativelink_simulation.rpt
...\.......\db\add_sub_9rh.tdf
...\.......\..\add_sub_jsh.tdf
...\.......\..\add_sub_lnh.tdf
...\.......\..\add_sub_lsh.tdf
...\.......\..\altsyncram_6bc1.tdf
...\.......\..\altsyncram_r1d1.tdf
...\.......\..\cpu.asm.qmsg
...\.......\..\cpu.asm.rdb
...\.......\..\cpu.cbx.xml
...\.......\..\cpu.cmp.bpm
...\.......\..\cpu.cmp.cdb
...\.......\..\cpu.cmp.ecobp
...\.......\..\cpu.cmp.hdb
...\.......\..\cpu.cmp.kpt
...\.......\..\cpu.cmp.logdb
...\.......\..\cpu.cmp.qrpt
...\.......\..\cpu.cmp.rdb
...\.......\..\cpu.cmp.tdb
...\.......\..\cpu.cmp0.ddb
...\.......\..\cpu.cmp_merge.kpt
...\.......\..\cpu.db_info
...\.......\..\cpu.eco.cdb
...\.......\..\cpu.eda.qmsg
...\.......\..\cpu.eds_overflow
...\.......\..\cpu.fit.qmsg
...\.......\..\cpu.fnsim.hdb
...\.......\..\cpu.fnsim.qmsg
...\.......\..\cpu.hier_info
...\.......\..\cpu.hif
...\.......\..\cpu.lpc.html
...\.......\..\cpu.lpc.rdb
...\.......\..\cpu.lpc.txt
...\.......\..\cpu.map.bpm
...\.......\..\cpu.map.cdb
...\.......\..\cpu.map.ecobp
...\.......\..\cpu.map.hdb
...\.......\..\cpu.map.kpt
...\.......\..\cpu.map.logdb
...\.......\..\cpu.map.qmsg
...\.......\..\cpu.map_bb.cdb
...\.......\..\cpu.map_bb.hdb
...\.......\..\cpu.map_bb.logdb
...\.......\..\cpu.mif_update.qmsg
...\.......\..\cpu.pre_map.cdb
...\.......\..\cpu.pre_map.hdb
...\.......\..\cpu.rpp.qmsg
...\.......\..\cpu.rtlv.hdb
...\.......\..\cpu.rtlv_sg.cdb
...\.......\..\cpu.rtlv_sg_swap.cdb
...\.......\..\cpu.sgate.rvd
...\.......\..\cpu.sgate_sm.rvd
...\.......\..\cpu.sgdiff.cdb
...\.......\..\cpu.sgdiff.hdb
...\.......\..\cpu.sim.cvwf
...\.......\..\cpu.sim.hdb
...\.......\..\cpu.sim.qmsg
...\.......\..\cpu.sim.rdb
...\.......\..\cpu.simfam
...\.......\..\cpu.sld_design_entry.sci
...\.......\..\cpu.sld_design_entry_dsc.sci
...\.......\..\cpu.smart_action.txt
...\.......\..\cpu.smp_dump.txt
...\.......\..\cpu.sta.qmsg
...\.......\..\cpu.sta.rdb
...\.......\..\cpu.syn_hier_info
...\.......\..\cpu.tan.qmsg
...\.......\..\cpu.taw.rdb