文件名称:CPU
- 所属分类：
- VHDL编程
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 2.07mb
- 下载次数：
- 0次
- 提 供 者：
- lisha*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
使用VHDL语言实现了一个两级流水线的CPU，-VHDL language using a two-stage pipeline of the CPU,
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CPU工程文件\CPU.bdf
...........\CPU.vhd
...........\PartReg1.bdf
...........\PartReg1.vhd
...........\PartReg2.bdf
...........\PartReg2.vhd
...........\PartReg3.vhd
...........\PartReg4.vhd
...........\PartRegIR.bdf
...........\PartRegIR.vhd
...........\PartRegPC.bdf
...........\PartRegPC.vhd
...........\PartSP.bdf
...........\PartSP.vhd
...........\RAMBLOCK.bdf
...........\RAMBLOCK.vhd
...........\CPU.qpf
...........\CPU.qsf
...........\CPU.map.eqn
...........\CPU.map.rpt
...........\CPU.flow.rpt
...........\CPU.map.summary
...........\CPU.done
...........\CPU.fit.eqn
...........\CPU.pin
...........\CPU.fit.rpt
...........\CPU.fit.summary
...........\CPU.sof
...........\CPU.pof
...........\CPU.asm.rpt
...........\CPU.tan.summary
...........\CPU.tan.rpt
...........\CPU.sim.rpt
...........\sim.cfg
...........\CPU.qws
...........\cmp_state.ini
...........\RAMBLOCK.bsf
...........\CPU.cdf
...........\TEST.vwf
...........\RAM\MEM_V_1_0.vhd
...........\...\db
...........\RAM
...........\VHDLCode\CLOCK_V_1_0.vhd
...........\........\COMP_V_1_0.vhd
...........\........\EXT4TO16.vhd
...........\........\Ext_Add_V_1_0.vhd
...........\........\JMP_COND_V_1_0.vhd
...........\........\MEM_CTRLER_V_1_0.vhd
...........\........\MEM_CTRLER_V_1_0.vhd.bak
...........\........\MRW_CTRL_V_1_0.vhd
...........\........\MUX16.cmp
...........\........\MUX16.vhd
...........\........\NOTGate.cmp
...........\........\NOTGate.vhd
...........\........\One_Adder.cmp
...........\........\One_Adder.vhd
...........\........\One_Suber.cmp
...........\........\One_Suber.vhd
...........\........\REG2_V_1_0.vhd
...........\........\REG3_V_1_0.vhd
...........\........\REG4_V_1_0.vhd
...........\........\REG_FLAG_V_1_0.vhd.bak
...........\........\REG_IR_V_1_0.vhd
...........\........\REG_PC_V_1_0.vhd
...........\........\REG_Selector.vhd
...........\........\RF_V_1_0.vhd
...........\........\SP_CALC_V_1_0.vhd
...........\........\StdAdder.cmp
...........\........\StdAdder.vhd
...........\........\StdCompare.cmp
...........\........\StdCompare.vhd
...........\........\TRIGate.cmp
...........\........\TRIGate.vhd
...........\........\REG_SP_V_1_0.vhd
...........\........\DECODER_V_1_0.vhd
...........\........\REG_FLAG_V_1_0.vhd
...........\........\db
...........\........\REG1_V_1_0.vhd
...........\........\CLKController.vhd
...........\........\CLK_Counter.vhd
...........\........\ALU_V_1_0.vhd
...........\VHDLCode
...........\db\CPU.db_info
...........\..\CPU.sim.qmsg
...........\..\CPU.sim.rdb
...........\..\CPU.hif
...........\..\CPU.sim.hdb
...........\..\mux_9bc.tdf
...........\..\add_sub_kfe.tdf
...........\..\add_sub_0ce.tdf
...........\..\CPU.sld_design_entry.sci
...........\..\add_sub_lge.tdf
...........\..\CPU.hier_info
...........\..\CPU.map.qmsg
...........\..\add_sub_kjh.tdf
...........\..\CPU.pre_map.hdb
...........\..\CPU.cmp.rdb
...........\..\CPU.sgdiff.cdb
...........\..\CPU.rtlv.hdb
...........\..\CPU.map.cdb
...........\CPU.vhd
...........\PartReg1.bdf
...........\PartReg1.vhd
...........\PartReg2.bdf
...........\PartReg2.vhd
...........\PartReg3.vhd
...........\PartReg4.vhd
...........\PartRegIR.bdf
...........\PartRegIR.vhd
...........\PartRegPC.bdf
...........\PartRegPC.vhd
...........\PartSP.bdf
...........\PartSP.vhd
...........\RAMBLOCK.bdf
...........\RAMBLOCK.vhd
...........\CPU.qpf
...........\CPU.qsf
...........\CPU.map.eqn
...........\CPU.map.rpt
...........\CPU.flow.rpt
...........\CPU.map.summary
...........\CPU.done
...........\CPU.fit.eqn
...........\CPU.pin
...........\CPU.fit.rpt
...........\CPU.fit.summary
...........\CPU.sof
...........\CPU.pof
...........\CPU.asm.rpt
...........\CPU.tan.summary
...........\CPU.tan.rpt
...........\CPU.sim.rpt
...........\sim.cfg
...........\CPU.qws
...........\cmp_state.ini
...........\RAMBLOCK.bsf
...........\CPU.cdf
...........\TEST.vwf
...........\RAM\MEM_V_1_0.vhd
...........\...\db
...........\RAM
...........\VHDLCode\CLOCK_V_1_0.vhd
...........\........\COMP_V_1_0.vhd
...........\........\EXT4TO16.vhd
...........\........\Ext_Add_V_1_0.vhd
...........\........\JMP_COND_V_1_0.vhd
...........\........\MEM_CTRLER_V_1_0.vhd
...........\........\MEM_CTRLER_V_1_0.vhd.bak
...........\........\MRW_CTRL_V_1_0.vhd
...........\........\MUX16.cmp
...........\........\MUX16.vhd
...........\........\NOTGate.cmp
...........\........\NOTGate.vhd
...........\........\One_Adder.cmp
...........\........\One_Adder.vhd
...........\........\One_Suber.cmp
...........\........\One_Suber.vhd
...........\........\REG2_V_1_0.vhd
...........\........\REG3_V_1_0.vhd
...........\........\REG4_V_1_0.vhd
...........\........\REG_FLAG_V_1_0.vhd.bak
...........\........\REG_IR_V_1_0.vhd
...........\........\REG_PC_V_1_0.vhd
...........\........\REG_Selector.vhd
...........\........\RF_V_1_0.vhd
...........\........\SP_CALC_V_1_0.vhd
...........\........\StdAdder.cmp
...........\........\StdAdder.vhd
...........\........\StdCompare.cmp
...........\........\StdCompare.vhd
...........\........\TRIGate.cmp
...........\........\TRIGate.vhd
...........\........\REG_SP_V_1_0.vhd
...........\........\DECODER_V_1_0.vhd
...........\........\REG_FLAG_V_1_0.vhd
...........\........\db
...........\........\REG1_V_1_0.vhd
...........\........\CLKController.vhd
...........\........\CLK_Counter.vhd
...........\........\ALU_V_1_0.vhd
...........\VHDLCode
...........\db\CPU.db_info
...........\..\CPU.sim.qmsg
...........\..\CPU.sim.rdb
...........\..\CPU.hif
...........\..\CPU.sim.hdb
...........\..\mux_9bc.tdf
...........\..\add_sub_kfe.tdf
...........\..\add_sub_0ce.tdf
...........\..\CPU.sld_design_entry.sci
...........\..\add_sub_lge.tdf
...........\..\CPU.hier_info
...........\..\CPU.map.qmsg
...........\..\add_sub_kjh.tdf
...........\..\CPU.pre_map.hdb
...........\..\CPU.cmp.rdb
...........\..\CPU.sgdiff.cdb
...........\..\CPU.rtlv.hdb
...........\..\CPU.map.cdb