文件名称:I2C_Verilog_Model
介绍说明－－下载内容均来自于网络，请自行研究使用
该源程序包是I2C的Verilog语言模型，包括以下4个部分：RTL源代码，测试平台，软件仿真代码，说明文件。-This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
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下载文件列表
I2C_Verilog_Model\bench\verilog\i2c_slave_model.v
.................\.....\.......\spi_slave_model.v
.................\.....\.......\tst_bench_top.v
.................\.....\.......\wb_master_model.v
.................\doc\i2c_specs.pdf
.................\rtl\verilog\i2c_master_bit_ctrl.v
.................\...\.......\i2c_master_byte_ctrl.v
.................\...\.......\i2c_master_defines.v
.................\...\.......\i2c_master_top.v
.................\...\.......\timescale.v
.................\sim\i2c_verilog\run\bench.vcd
.................\...\...........\...\ncverilog.key
.................\...\...........\...\ncverilog.log
.................\...\...........\...\run
.................\...\...........\...\INCA_libs
.................\...\...........\...\waves
.................\...\...........\run
.................\bench\verilog
.................\rtl\verilog
.................\sim\i2c_verilog
.................\bench
.................\doc
.................\rtl
.................\sim
I2C_Verilog_Model
.................\.....\.......\spi_slave_model.v
.................\.....\.......\tst_bench_top.v
.................\.....\.......\wb_master_model.v
.................\doc\i2c_specs.pdf
.................\rtl\verilog\i2c_master_bit_ctrl.v
.................\...\.......\i2c_master_byte_ctrl.v
.................\...\.......\i2c_master_defines.v
.................\...\.......\i2c_master_top.v
.................\...\.......\timescale.v
.................\sim\i2c_verilog\run\bench.vcd
.................\...\...........\...\ncverilog.key
.................\...\...........\...\ncverilog.log
.................\...\...........\...\run
.................\...\...........\...\INCA_libs
.................\...\...........\...\waves
.................\...\...........\run
.................\bench\verilog
.................\rtl\verilog
.................\sim\i2c_verilog
.................\bench
.................\doc
.................\rtl
.................\sim
I2C_Verilog_Model