文件名称:Counter-60
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In this example, counter 60 is implemented as part of the real time clock time electronic clocks. Done in the platform mentor Graphics and describes in the VHDL code. This counter has a role to the front edge of every 60 clock sends a signal following the counter.
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下载文件列表
Projekat 2 Peca\ivan.vhd
...............\Milenkovic Ivan 12650.doc
...............\Milenkovic Ivan 12650.docx
...............\PEK-PZ00-10 Brava.doc
...............\portovi.JPG
...............\Projekat 2.ppt
...............\Projekat 2.pptx
...............\slika 1.JPG
...............\slika 2.JPG
...............\slika 3.JPG
...............\slika 4.JPG
...............\slika 5.JPG
...............\slika 6.JPG
...............\slika 7.JPG
...............\slika 8.JPG
...............\~WRL0684.tmp
Projekat 2 Peca
...............\Milenkovic Ivan 12650.doc
...............\Milenkovic Ivan 12650.docx
...............\PEK-PZ00-10 Brava.doc
...............\portovi.JPG
...............\Projekat 2.ppt
...............\Projekat 2.pptx
...............\slika 1.JPG
...............\slika 2.JPG
...............\slika 3.JPG
...............\slika 4.JPG
...............\slika 5.JPG
...............\slika 6.JPG
...............\slika 7.JPG
...............\slika 8.JPG
...............\~WRL0684.tmp
Projekat 2 Peca