文件名称:TEST5
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8位硬件加法器设计
熟悉Quartus II的VHDL文本设计流程全过程,学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design
Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
熟悉Quartus II的VHDL文本设计流程全过程,学习简单时序电路的设计、仿真和测试。-eight bit Hardware adder design
Familiar with Quartus II VHDL text design flow process, learn the simple sequential circuits design, simulation and testing
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下载文件列表
TEST5\BCDADD.asm.rpt
.....\BCDADD.bdf
.....\BCDADD.done
.....\BCDADD.fit.rpt
.....\BCDADD.fit.summary
.....\BCDADD.flow.rpt
.....\BCDADD.map.rpt
.....\BCDADD.map.summary
.....\BCDADD.pin
.....\BCDADD.qpf
.....\BCDADD.qsf
.....\BCDADD.qws
.....\BCDADD.tan.rpt
.....\BCDADD.tan.summary
.....\BCDADD4.bsf
.....\BCDADD4.vhd
.....\BCDADD_assignment_defaults.qdf
.....\db\add_sub_pjh.tdf
.....\..\BCDADD.db_info
.....\..\BCDADD.eco.cdb
.....\..\BCDADD.sld_design_entry.sci
.....\db
TEST5
.....\BCDADD.bdf
.....\BCDADD.done
.....\BCDADD.fit.rpt
.....\BCDADD.fit.summary
.....\BCDADD.flow.rpt
.....\BCDADD.map.rpt
.....\BCDADD.map.summary
.....\BCDADD.pin
.....\BCDADD.qpf
.....\BCDADD.qsf
.....\BCDADD.qws
.....\BCDADD.tan.rpt
.....\BCDADD.tan.summary
.....\BCDADD4.bsf
.....\BCDADD4.vhd
.....\BCDADD_assignment_defaults.qdf
.....\db\add_sub_pjh.tdf
.....\..\BCDADD.db_info
.....\..\BCDADD.eco.cdb
.....\..\BCDADD.sld_design_entry.sci
.....\db
TEST5