文件名称:S5_UART
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1 基于altera FPGA EP1C12 实现UART传输功能-1 UART transmission function Based on altera FPGA EP1C12
相关搜索： EP1C12
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下载文件列表
S5_UART\Doc\UART控制器设计说明.doc
.......\func_sim\rcvr.v
.......\........\transcript
.......\........\txmit.v
.......\........\txmit_tf.do
.......\........\uart.cr.mti
.......\........\uart.mpf
.......\........\uart.v
.......\........\uart_if.v
.......\........\uart_tb.do
.......\........\uart_tb.v
.......\........\uart_tb_fixed.do
.......\........\vish_stacktrace.vstf
.......\........\vsim.wlf
.......\........\wave.do
.......\........\.ork\@u@a@r@t_tb\verilog.asm
.......\........\....\...........\_primary.dat
.......\........\....\...........\_primary.vhd
.......\........\....\rcvr\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\txmit\verilog.asm
.......\........\....\.....\_primary.dat
.......\........\....\.....\_primary.vhd
.......\........\....\uart\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\...._if\verilog.asm
.......\........\....\.......\_primary.dat
.......\........\....\.......\_primary.vhd
.......\........\....\_info
.......\........\....\@u@a@r@t_tb
.......\........\....\rcvr
.......\........\....\txmit
.......\........\....\uart
.......\........\....\uart_if
.......\........\work
.......\Doc
.......\func_sim
S5_UART
.......\func_sim\rcvr.v
.......\........\transcript
.......\........\txmit.v
.......\........\txmit_tf.do
.......\........\uart.cr.mti
.......\........\uart.mpf
.......\........\uart.v
.......\........\uart_if.v
.......\........\uart_tb.do
.......\........\uart_tb.v
.......\........\uart_tb_fixed.do
.......\........\vish_stacktrace.vstf
.......\........\vsim.wlf
.......\........\wave.do
.......\........\.ork\@u@a@r@t_tb\verilog.asm
.......\........\....\...........\_primary.dat
.......\........\....\...........\_primary.vhd
.......\........\....\rcvr\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\txmit\verilog.asm
.......\........\....\.....\_primary.dat
.......\........\....\.....\_primary.vhd
.......\........\....\uart\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\...._if\verilog.asm
.......\........\....\.......\_primary.dat
.......\........\....\.......\_primary.vhd
.......\........\....\_info
.......\........\....\@u@a@r@t_tb
.......\........\....\rcvr
.......\........\....\txmit
.......\........\....\uart
.......\........\....\uart_if
.......\........\work
.......\Doc
.......\func_sim
S5_UART