收藏

文件名称:clock-synchronized-registers

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [WORD]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 88kb
  • 下载次数：
  • 0次
  • 提 供 者：
  • 李*
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
修正介绍说明

介绍说明－－下载内容均来自于网络，请自行研究使用

一般来说，CPU的读写时钟会引入到PLD中，笔者利用CPU的读写时钟实现同步读写寄存器，提高设计的可靠性。因此这种建模方式是推荐的CPU读写PLD寄存器建模方式-In general, CPU clock will read and write the introduction to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve design reliability. This modeling approach is therefore recommended to read and write CPU registers modeling methods PLD
(系统自动生成,下载前可以参看下载内容)

下载文件列表

使用CPU读写时钟同步方式读写PLD寄存器\asyn_bad\asyn_bad.prd

....................................\........\asyn_bad.prj

....................................\........\decode.v

....................................\........\read_reg.v

....................................\........\..v_1\AutoConstraint_top.sdc

....................................\........\.....\decode.edn

....................................\........\.....\decode.fse

....................................\........\.....\decode.prf

....................................\........\.....\decode.srm

....................................\........\.....\decode.srr

....................................\........\.....\decode.srs

....................................\........\.....\decode.tlg

....................................\........\.....\generic.fse

....................................\........\.....\generic.srd

....................................\........\.....\syntmp\decode.msg

....................................\........\.....\......\decode.plg

....................................\........\top.v

....................................\........\write_reg.v

....................................\oe_edge\decode.v

....................................\.......\oe_edge.prd

....................................\.......\oe_edge.prj

....................................\.......\read_reg.v

....................................\.......\..v_2\AutoConstraint_top.sdc

....................................\.......\.....\generic.fse

....................................\.......\.....\generic.srd

....................................\.......\.....\syntmp\top.msg

....................................\.......\.....\......\top.plg

....................................\.......\.....\top.edn

....................................\.......\.....\top.fse

....................................\.......\.....\top.prf

....................................\.......\.....\top.srm

....................................\.......\.....\top.srr

....................................\.......\.....\top.srs

....................................\.......\.....\top.tlg

....................................\.......\top.v

....................................\.......\write_reg.v

....................................\syn_wr\decode.v

....................................\......\read_reg.v

....................................\......\..v_1\generic.fse

....................................\......\.....\generic.srd

....................................\......\.....\syntmp\top.msg

....................................\......\.....\......\top.plg

....................................\......\.....\top.edn

....................................\......\.....\top.fse

....................................\......\.....\top.prf

....................................\......\.....\top.srm

....................................\......\.....\top.srr

....................................\......\.....\top.srs

....................................\......\.....\top.tlg

....................................\......\syntmp.msg

....................................\......\syn_wr.prd

....................................\......\syn_wr.prj

....................................\......\top.v

....................................\......\write_reg.v

....................................\说明.doc

....................................\asyn_bad\rev_1\syntmp

....................................\oe_edge\rev_2\syntmp

....................................\syn_wr\rev_1\syntmp

....................................\asyn_bad\rev_1

....................................\oe_edge\rev_2

....................................\syn_wr\rev_1

....................................\asyn_bad

....................................\oe_edge

....................................\syn_wr

使用CPU读写时钟同步方式读写PLD寄存器

相关说明

  • 本站资源为会员上传分享交流与学习,如有侵犯您的权益,请联系我们删除.
  • 本站是交换下载平台，提供交流渠道，下载内容来自于网络，除下载问题外，其它问题请自行百度。更多...
  • 请直接用浏览器下载本站内容，不要使用迅雷之类的下载软件，用WinRAR最新版进行解压.
  • 如果您发现内容无法下载，请稍后再次尝试；或者到消费记录里找到下载记录反馈给我们.
  • 下载后发现下载的内容跟说明不相乎，请到消费记录里找到下载记录反馈给我们，经确认后退回积分.
  • 如下载前有疑问，可以通过点击"提供者"的名字，查看对方的联系方式，联系对方咨询.
查看所有评论

相关评论

暂无评论内容．

发表评论

*主　　题：
*内　　容：
*验 证 码：

源码中国 www.ymcn.org