文件名称:S5_UART

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.06mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • blu****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

红色飓风的uart程序,我买的开发板的网站的历程-Red Hurricane uart procedure, I bought the course of the development board' s website
(系统自动生成,下载前可以参看下载内容)

下载文件列表

S5_UART\Doc\sscom.ini

.......\...\sscom32.exe

.......\...\UART控制器设计说明.doc

.......\...\xapp341.pdf

.......\func_sim\rcvr.v

.......\........\transcript

.......\........\txmit.v

.......\........\txmit_tf.do

.......\........\uart.cr.mti

.......\........\uart.mpf

.......\........\uart.v

.......\........\uart_if.v

.......\........\uart_tb.do

.......\........\uart_tb.v

.......\........\uart_tb_fixed.do

.......\........\vish_stacktrace.vstf

.......\........\vsim.wlf

.......\........\wave.do

.......\........\.ork\@u@a@r@t_tb\verilog.asm

.......\........\....\...........\_primary.dat

.......\........\....\...........\_primary.vhd

.......\........\....\rcvr\verilog.asm

.......\........\....\....\_primary.dat

.......\........\....\....\_primary.vhd

.......\........\....\txmit\verilog.asm

.......\........\....\.....\_primary.dat

.......\........\....\.....\_primary.vhd

.......\........\....\uart\verilog.asm

.......\........\....\....\_primary.dat

.......\........\....\....\_primary.vhd

.......\........\....\...._if\verilog.asm

.......\........\....\.......\_primary.dat

.......\........\....\.......\_primary.vhd

.......\........\....\_info

.......\physical\altclklock0.bsf

.......\........\altclklock0.v

.......\........\altclklock0_bb.v

.......\........\async_transmitter.bsf

.......\........\cmp_state.ini

.......\........\div.bsf

.......\........\div_2.bsf

.......\........\div_2.v

.......\........\filter.bsf

.......\........\LED_flush.bsf

.......\........\rcvr.bsf

.......\........\simulation\modelsim\cyclone_atoms.v

.......\........\..........\........\uart_if.vo

.......\........\..........\........\uart_if_modelsim.xrf

.......\........\..........\........\uart_if_v.sdo

.......\........\..........\........\uart_post.cr.mti

.......\........\..........\........\uart_post.mpf

.......\........\..........\........\work\@p@r@i@m_@d@f@f@e\verilog.asm

.......\........\..........\........\....\.................\_primary.dat

.......\........\..........\........\....\.................\_primary.vhd

.......\........\..........\........\....\.u@a@r@t_tb\verilog.asm

.......\........\..........\........\....\...........\_primary.dat

.......\........\..........\........\....\...........\_primary.vhd

.......\........\..........\........\....\and1\verilog.asm

.......\........\..........\........\....\....\_primary.dat

.......\........\..........\........\....\....\_primary.vhd

.......\........\..........\........\....\....6\verilog.asm

.......\........\..........\........\....\.....\_primary.dat

.......\........\..........\........\....\.....\_primary.vhd

.......\........\..........\........\....\b17mux21\verilog.asm

.......\........\..........\........\....\........\_primary.dat

.......\........\..........\........\....\........\_primary.vhd

.......\........\..........\........\....\.5mux21\verilog.asm

.......\........\..........\........\....\.......\_primary.dat

.......\........\..........\........\....\.......\_primary.vhd

.......\........\..........\........\....\.mux21\verilog.asm

.......\........\..........\........\....\......\_primary.dat

.......\........\..........\........\....\......\_primary.vhd

.......\........\..........\........\....\cyclone_asmiblock\verilog.asm

.......\........\..........\........\....\.................\_primary.dat

.......\........\..........\........\....\.................\_primary.vhd

.......\........\..........\........\....\..........ynch_io\verilog.asm

.......\........\..........\........\....\.................\_primary.dat

.......\........\..........\........\....\.................\_primary.vhd

.......\........\..........\........\....\...............lcell\verilog.asm

.......\........\..........\........\....\....................\_primary.dat

.......\........\..........\........\....\....................\_primary.vhd

.......\........\..........\........\....\........crcblock\verilog.asm

.......\........\..........\........\....\................\_primary.dat

.......\........\..........\........\....\................\_primary.vhd

.......\........\..........\........\....\........dll\verilog.asm

.......\.....

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