文件名称:verilog_sdram_controller_testbench
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SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
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下载文件列表
verilog\func_sim\func_sim.cfg
.......\........\func_sim.log
.......\........\func_sim.vpd
.......\........\glbl.v
.......\........\run.bat
.......\........\run_sim
.......\........\s.alias
.......\........\sim.bat
.......\........\sim.do
.......\........\src.f
.......\........\states.alias
.......\........\string_decode_fn.v
.......\........\tb_sdrm.v
.......\micron\bank0.txt
.......\......\bank1.txt
.......\......\mt48lc1m16a1-8a.v
.......\......\mt48lc1m16a1.v
.......\......\test.v
.......\par\run_par
.......\...\sdrm.edf
.......\...\sdrm.ucf
.......\...\sdrm_par.sdf
.......\...\sdrm_par.v
.......\.ost_route\post_route.cfg
.......\..........\post_route.log
.......\..........\post_route.vpd
.......\..........\run_sim
.......\..........\sdrm_par.sdf
.......\..........\sdrm_par.v
.......\..........\string_decode_post_route.v
.......\..........\tb_post_route.v
.......\README
.......\sim.bat
.......\.rc\brst_cntr.v
.......\...\cslt_cntr.v
.......\...\define.v
.......\...\glbl.v
.......\...\ki_cntr.v
.......\...\rcd_cntr.v
.......\...\ref_cntr.v
.......\...\sdrm.v
.......\...\sdrmc_state.v
.......\...\sdrm_t.v
.......\...\sys_int.v
.......\...\xilinx\BUFG.v
.......\...\......\CLKDLL.v
.......\...\......\glbl.v
.......\...\......\IBUF.v
.......\...\......\IBUFG.v
.......\...\......\IOBUF_F_12.v
.......\...\......\OBUF_F_12.v
.......\...\......\OBUF_F_16.v
.......\...\......\SRL16.v
.......\src.f
.......\.ynth\run_synth
.......\.....\sdrm.edf
.......\.....\sdrm.scr
.......\.....\setup.scr
.......\.rc\xilinx
.......\func_sim
.......\micron
.......\par
.......\post_route
.......\src
.......\synth
verilog
.......\........\func_sim.log
.......\........\func_sim.vpd
.......\........\glbl.v
.......\........\run.bat
.......\........\run_sim
.......\........\s.alias
.......\........\sim.bat
.......\........\sim.do
.......\........\src.f
.......\........\states.alias
.......\........\string_decode_fn.v
.......\........\tb_sdrm.v
.......\micron\bank0.txt
.......\......\bank1.txt
.......\......\mt48lc1m16a1-8a.v
.......\......\mt48lc1m16a1.v
.......\......\test.v
.......\par\run_par
.......\...\sdrm.edf
.......\...\sdrm.ucf
.......\...\sdrm_par.sdf
.......\...\sdrm_par.v
.......\.ost_route\post_route.cfg
.......\..........\post_route.log
.......\..........\post_route.vpd
.......\..........\run_sim
.......\..........\sdrm_par.sdf
.......\..........\sdrm_par.v
.......\..........\string_decode_post_route.v
.......\..........\tb_post_route.v
.......\README
.......\sim.bat
.......\.rc\brst_cntr.v
.......\...\cslt_cntr.v
.......\...\define.v
.......\...\glbl.v
.......\...\ki_cntr.v
.......\...\rcd_cntr.v
.......\...\ref_cntr.v
.......\...\sdrm.v
.......\...\sdrmc_state.v
.......\...\sdrm_t.v
.......\...\sys_int.v
.......\...\xilinx\BUFG.v
.......\...\......\CLKDLL.v
.......\...\......\glbl.v
.......\...\......\IBUF.v
.......\...\......\IBUFG.v
.......\...\......\IOBUF_F_12.v
.......\...\......\OBUF_F_12.v
.......\...\......\OBUF_F_16.v
.......\...\......\SRL16.v
.......\src.f
.......\.ynth\run_synth
.......\.....\sdrm.edf
.......\.....\sdrm.scr
.......\.....\setup.scr
.......\.rc\xilinx
.......\func_sim
.......\micron
.......\par
.......\post_route
.......\src
.......\synth
verilog