文件名称:XAPP134_SDRAM_VHDL

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.94mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • j*
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  • 别用迅雷下载,失败请重下,重下不扣分!

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XAPP134 SDRAM VHDL design file
(系统自动生成,下载前可以参看下载内容)

下载文件列表

XAPP134_SDRAM_VHDL\vhdl\func_sim\brst_cntr.vhd

..................\....\........\cslt_cntr.vhd

..................\....\........\ki_cntr.vhd

..................\....\........\load.do

..................\....\........\mt48lc1m16a1.v

..................\....\........\mti_pkg.vhd

..................\....\........\rcd_cntr.vhd

..................\....\........\ref_cntr.vhd

..................\....\........\run_sim.do

..................\....\........\sdrm.vhd

..................\....\........\sdrmc_state.vhd

..................\....\........\sdrm_t.vhd

..................\....\........\state.do

..................\....\........\sys_int.vhd

..................\....\........\tb_sdrm.v

..................\....\........\transcript

..................\....\........\verwave.do

..................\....\........\work\brst_cntr\brst_cntr_arch.asm

..................\....\........\....\.........\brst_cntr_arch.dat

..................\....\........\....\.........\_primary.dat

..................\....\........\....\cslt_cntr\cslt_cntr_arch.asm

..................\....\........\....\.........\cslt_cntr_arch.dat

..................\....\........\....\.........\_primary.dat

..................\....\........\....\ki_cntr\ki_cntr_arch.asm

..................\....\........\....\.......\ki_cntr_arch.dat

..................\....\........\....\.......\_primary.dat

..................\....\........\....\mt48lc1m16a1\verilog.asm

..................\....\........\....\............\_primary.dat

..................\....\........\....\............\_primary.vhd

..................\....\........\....\..i_pkg\body.asm

..................\....\........\....\.......\body.dat

..................\....\........\....\.......\_primary.dat

..................\....\........\....\.......\_vhdl.asm

..................\....\........\....\rcd_cntr\rcd_cntr_arch.asm

..................\....\........\....\........\rcd_cntr_arch.dat

..................\....\........\....\........\_primary.dat

..................\....\........\....\.ef_cntr\ref_cntr_arch.asm

..................\....\........\....\........\ref_cntr_arch.dat

..................\....\........\....\........\_primary.dat

..................\....\........\....\sdrm\sdrm_arch.asm

..................\....\........\....\....\sdrm_arch.dat

..................\....\........\....\....\_primary.dat

..................\....\........\....\....c_state\sdrmc_state_arch.asm

..................\....\........\....\...........\sdrmc_state_arch.dat

..................\....\........\....\...........\_primary.dat

..................\....\........\....\...._t\sdrm_t_arch.asm

..................\....\........\....\......\sdrm_t_arch.dat

..................\....\........\....\......\_primary.dat

..................\....\........\....\.ys_int\sys_int_arch.asm

..................\....\........\....\.......\sys_int_arch.dat

..................\....\........\....\.......\_primary.dat

..................\....\........\....\t_sdrm\testbench.asm

..................\....\........\....\......\testbench.dat

..................\....\........\....\......\verilog.asm

..................\....\........\....\......\_primary.dat

..................\....\........\....\......\_primary.vhd

..................\....\........\....\_info

..................\....\micron\bank0.txt

..................\....\......\bank1.txt

..................\....\......\mt48lc1m16a1-8a.v

..................\....\......\mt48lc1m16a1.v

..................\....\......\test.v

..................\....\par\sdrm.bit

..................\....\...\sdrm.edf

..................\....\...\sdrm.ll

..................\....\...\sdrm.ncf

..................\....\...\xproj\sdrm.xpj

..................\....\...\.....\ver1\netlist.lst

..................\....\...\.....\....\rev1\bitgen.ut

..................\....\...\.....\....\....\command.his

..................\....\...\.....\....\....\fe.log

..................\....\...\.....\....\....\map.mrp

..................\....\...\.....\....\....\map.ncd

..................\....\...\.....\....\....\map.ngm

..................\....\...\.....\....\....\ngd2ver.log

..................\....\...\.....\....\....\ngd2vhdl.log

..

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