文件名称:chapter4
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog HDL的通信系統源代码范例
(系统自动生成,下载前可以参看下载内容)
下载文件列表
chapter4\add_full.v
........\add_half.v
........\count16.v
........\decode3to8.v
........\fifo3.v
........\fre13.v
........\mult1from8.v
........\ram_4_4.v
........\rom_16_4.v
........\ser_to_parr.v
........\trigger_d.v
........\trigger_jk.v
........\trigger_rs.v
chapter4
........\add_half.v
........\count16.v
........\decode3to8.v
........\fifo3.v
........\fre13.v
........\mult1from8.v
........\ram_4_4.v
........\rom_16_4.v
........\ser_to_parr.v
........\trigger_d.v
........\trigger_jk.v
........\trigger_rs.v
chapter4