文件名称:shiziluoji
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三位二进制加1与加2计数器 :三位二进制模5计数器。当外部输入X = 1时,计数器加2计数;外部输入X = 0时,计数器加1计数。“模5”为逢“5”进1计数。
原始条件:使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 ),设计三位二进制模5计数器。
-The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X = 1 when the external input, the counter plus 2 counts external input X = 0, the counter by 1 count. " Die 5" for every " 5" into a count. Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
原始条件:使用D触发器( 74 LS 74 )、“与”门 ( 74 LS 08 )、“或”门( 74 LS 32 )、非门 ( 74 LS 04 ),设计三位二进制模5计数器。
-The three binary counter plus 1 and plus 2 : three binary mod 5 counter. X = 1 when the external input, the counter plus 2 counts external input X = 0, the counter by 1 count. " Die 5" for every " 5" into a count. Original conditions: Use D flip-flop (74 LS 74), " and" gate (74 LS 08), " or" gate (74 LS 32), non-gate (74 LS 04), three binary mod 5 counter design.
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