文件名称:SASA
介绍说明－－下载内容均来自于网络，请自行研究使用
串口程序，一共有四个模块名，波特率为1，包括接受，发送模块-Serial program, a total of four module name, the baud rate is 1, including the acceptance, sending module
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ninini\ninini.npl
......\fredivn.vhdl
......\__projnav.log
......\automake.log
......\fredivn.prj
......\fredivn.cmd_log
......\fredivn.syr
......\fredivn.lso
......\fredivn.stx
......\rxd3.vhdl
......\rxd3.prj
......\rxd3.cmd_log
......\rxd3.syr
......\rxd3.lso
......\rxd3.stx
......\txd5.vhdl
......\txd5.prj
......\txd5.cmd_log
......\txd5.syr
......\txd5.lso
......\txd5.ngr
......\txd5.ngc
......\txd5.stx
......\all.vhdl
......\D_flipflop.vhdl
......\coregen.log
......\coregen.prj
......\ewe.vhdl
......\ewe.prj
......\ewe.cmd_log
......\ewe.syr
......\ewe.lso
......\ewe.stx
......\only.vhdl
......\test_uart_top.prj
......\test_uart_top.cmd_log
......\test_uart_top.syr
......\test_uart_top_vhdl.prj
......\test_uart_top.lso
......\fredivn.ngr
......\fredivn.ngc
......\baud.vhdl
......\send.vhdl
......\recv.vhdl
......\ctrl.vhdl
......\alll.vhdl
......\rxd3.ngr
......\rxd3.ngc
......\recv.prj
......\recv.cmd_log
......\recv.syr
......\recv.lso
......\recv.stx
......\ewe.ngr
......\ewe.ngc
......\total_part.vhdl
......\ER.vhdl
......\xst\work\hdllib.ref
......\...\....\sub00\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\...\....\.....\vhpl02.vho
......\...\....\.....\vhpl03.vho
......\...\....\.....\vhpl04.vho
......\...\....\.....\vhpl05.vho
......\...\....\.....\vhpl06.vho
......\...\....\.....\vhpl07.vho
......\...\....\.....\vhpl08.vho
......\...\....\.....\vhpl09.vho
......\...\....\.....\vhpl10.vho
......\...\....\.....\vhpl11.vho
......\...\....\.....\vhpl12.vho
......\...\....\.....\vhpl13.vho
......\...\....\.....\vhpl14.vho
......\...\....\.....\vhpl15.vho
......\...\....\.....\vhpl16.vho
......\...\....\.....\vhpl17.vho
......\...\....\.....\vhpl18.vho
......\...\....\hdpdeps.ref
......\__projnav\runXst_tcl.rsp
......\.........\ninini_flowplus.gfl
......\.........\ninini.gfl
......\.........\fredivn.xst
......\.........\rxd3.xst
......\.........\txd5.xst
......\.........\coregen.rsp
......\.........\ewe.xst
......\.........\test_uart_top.xst
......\.........\recv.xst
......\.........\baud.xst
......\.........\cpu.xst
......\.........\er.xst
......\.........\send.xst
......\.........\hb_cmds
......\.........\ctrl.xst
......\.........\parentEditConstraintsTextApp_tcl.rsp
......\.........\ednTOngd_tcl.rsp
......\.........\nc1TOncd_tcl.rsp
......\.........\er_ncdTOut_tcl.rsp
......\.........\posttrc.log
......\.........\bitgen.rsp
......\fredivn.vhdl
......\__projnav.log
......\automake.log
......\fredivn.prj
......\fredivn.cmd_log
......\fredivn.syr
......\fredivn.lso
......\fredivn.stx
......\rxd3.vhdl
......\rxd3.prj
......\rxd3.cmd_log
......\rxd3.syr
......\rxd3.lso
......\rxd3.stx
......\txd5.vhdl
......\txd5.prj
......\txd5.cmd_log
......\txd5.syr
......\txd5.lso
......\txd5.ngr
......\txd5.ngc
......\txd5.stx
......\all.vhdl
......\D_flipflop.vhdl
......\coregen.log
......\coregen.prj
......\ewe.vhdl
......\ewe.prj
......\ewe.cmd_log
......\ewe.syr
......\ewe.lso
......\ewe.stx
......\only.vhdl
......\test_uart_top.prj
......\test_uart_top.cmd_log
......\test_uart_top.syr
......\test_uart_top_vhdl.prj
......\test_uart_top.lso
......\fredivn.ngr
......\fredivn.ngc
......\baud.vhdl
......\send.vhdl
......\recv.vhdl
......\ctrl.vhdl
......\alll.vhdl
......\rxd3.ngr
......\rxd3.ngc
......\recv.prj
......\recv.cmd_log
......\recv.syr
......\recv.lso
......\recv.stx
......\ewe.ngr
......\ewe.ngc
......\total_part.vhdl
......\ER.vhdl
......\xst\work\hdllib.ref
......\...\....\sub00\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\...\....\.....\vhpl02.vho
......\...\....\.....\vhpl03.vho
......\...\....\.....\vhpl04.vho
......\...\....\.....\vhpl05.vho
......\...\....\.....\vhpl06.vho
......\...\....\.....\vhpl07.vho
......\...\....\.....\vhpl08.vho
......\...\....\.....\vhpl09.vho
......\...\....\.....\vhpl10.vho
......\...\....\.....\vhpl11.vho
......\...\....\.....\vhpl12.vho
......\...\....\.....\vhpl13.vho
......\...\....\.....\vhpl14.vho
......\...\....\.....\vhpl15.vho
......\...\....\.....\vhpl16.vho
......\...\....\.....\vhpl17.vho
......\...\....\.....\vhpl18.vho
......\...\....\hdpdeps.ref
......\__projnav\runXst_tcl.rsp
......\.........\ninini_flowplus.gfl
......\.........\ninini.gfl
......\.........\fredivn.xst
......\.........\rxd3.xst
......\.........\txd5.xst
......\.........\coregen.rsp
......\.........\ewe.xst
......\.........\test_uart_top.xst
......\.........\recv.xst
......\.........\baud.xst
......\.........\cpu.xst
......\.........\er.xst
......\.........\send.xst
......\.........\hb_cmds
......\.........\ctrl.xst
......\.........\parentEditConstraintsTextApp_tcl.rsp
......\.........\ednTOngd_tcl.rsp
......\.........\nc1TOncd_tcl.rsp
......\.........\er_ncdTOut_tcl.rsp
......\.........\posttrc.log
......\.........\bitgen.rsp