文件名称:CY7C68013FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
USB控制芯片cy7c68013与FPGA通过slave fifo方式通信，块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CY7C68013FPGA\BulkIn\automake.log
.............\......\bitgen.ut
.............\......\coregen.log
.............\......\coregen.prj
.............\......\FPGA.dhp
.............\......\ISE编程顺序.txt
.............\......\top.cmd_log
.............\......\top.mrp
.............\......\top.msd
.............\......\top.msk
.............\......\top.ngm
.............\......\top.pcf
.............\......\top.rbb
.............\......\top.rbd
.............\......\top.ut
.............\......\Top.vhdl
.............\......\top_clk分频.txt
.............\......\top_last_par.ncd
.............\......\ucf.ucf
.............\......\_impact.cmd
.............\......\_impact.log
.............\......\.ngo\netlist.lst
.............\......\__projnav.log
.............\......\FPGA_ise12migration.zip
.............\......\FPGA.xise
.............\......\_xmsgs\pn_parser.xmsgs
.............\......\......\xst.xmsgs
.............\......\......\ngdbuild.xmsgs
.............\......\......\map.xmsgs
.............\......\......\par.xmsgs
.............\......\......\trce.xmsgs
.............\......\......\netgen.xmsgs
.............\......\......\bitgen.xmsgs
.............\......\FPGA.gise
.............\......\iseconfig\top.xreport
.............\......\.........\FPGA.projectmgr
.............\......\top_summary.html
.............\......\top.prj
.............\......\xst\work\sub00\vhpl00.vho
.............\......\...\....\.....\vhpl01.vho
.............\......\...\....\hdllib.ref
.............\......\...\....\hdpdeps.ref
.............\......\top.xst
.............\......\webtalk_pn.xml
.............\......\top.syr
.............\......\top.lso
.............\......\top_vhdl.prj
.............\......\top.ngr
.............\......\top.ngc
.............\......\top_xst.xrpt
.............\......\top.stx
.............\......\top.spl
.............\......\pepExtractor.prj
.............\......\top.sym
.............\......\top.bld
.............\......\xlnx_auto_0_xdb\cst.xbcd
.............\......\top_ngdbuild.xrpt
.............\......\top.ngd
.............\......\top_map.map
.............\......\top_map.ngm
.............\......\top_map.ncd
.............\......\top_map.mrp
.............\......\top_map.xrpt
.............\......\top.par
.............\......\top.ptwx
.............\......\top_pad.csv
.............\......\top.pad
.............\......\top_pad.txt
.............\......\top.unroutes
.............\......\top.ncd
.............\......\top.xpi
.............\......\top_par.xrpt
.............\......\top_guide.ncd
.............\......\top.twx
.............\......\top.twr
.............\......\netgen\synthesis\top_synthesis.nlf
.............\......\......\.........\top_synthesis.v
.............\......\top_envsettings.html
.............\......\top.bgn
.............\......\top.drc
.............\......\top.bit
.............\......\top_bitgen.xwbt
.............\......\top_usage.xml
.............\......\top_summary.xml
.............\......\usage_statistics_webtalk.html
.............\......\webtalk.log
.............\......\KKKK.cpj
.............\....Out\automake.log
.............\.......\bitgen.ut
.............\.......\coregen.log
.............\.......\coregen.prj
.............\.......\FPGA.dhp
.............\.......\prom.mcs
.............\.......\prom.prm
.............\.......\prom.sig
.............\.......\top.cmd_log
.............\.......\top.ll
.............\.......\top.mrp
.............\.......\top.msd
.............\.......\top.msk
.............\......\bitgen.ut
.............\......\coregen.log
.............\......\coregen.prj
.............\......\FPGA.dhp
.............\......\ISE编程顺序.txt
.............\......\top.cmd_log
.............\......\top.mrp
.............\......\top.msd
.............\......\top.msk
.............\......\top.ngm
.............\......\top.pcf
.............\......\top.rbb
.............\......\top.rbd
.............\......\top.ut
.............\......\Top.vhdl
.............\......\top_clk分频.txt
.............\......\top_last_par.ncd
.............\......\ucf.ucf
.............\......\_impact.cmd
.............\......\_impact.log
.............\......\.ngo\netlist.lst
.............\......\__projnav.log
.............\......\FPGA_ise12migration.zip
.............\......\FPGA.xise
.............\......\_xmsgs\pn_parser.xmsgs
.............\......\......\xst.xmsgs
.............\......\......\ngdbuild.xmsgs
.............\......\......\map.xmsgs
.............\......\......\par.xmsgs
.............\......\......\trce.xmsgs
.............\......\......\netgen.xmsgs
.............\......\......\bitgen.xmsgs
.............\......\FPGA.gise
.............\......\iseconfig\top.xreport
.............\......\.........\FPGA.projectmgr
.............\......\top_summary.html
.............\......\top.prj
.............\......\xst\work\sub00\vhpl00.vho
.............\......\...\....\.....\vhpl01.vho
.............\......\...\....\hdllib.ref
.............\......\...\....\hdpdeps.ref
.............\......\top.xst
.............\......\webtalk_pn.xml
.............\......\top.syr
.............\......\top.lso
.............\......\top_vhdl.prj
.............\......\top.ngr
.............\......\top.ngc
.............\......\top_xst.xrpt
.............\......\top.stx
.............\......\top.spl
.............\......\pepExtractor.prj
.............\......\top.sym
.............\......\top.bld
.............\......\xlnx_auto_0_xdb\cst.xbcd
.............\......\top_ngdbuild.xrpt
.............\......\top.ngd
.............\......\top_map.map
.............\......\top_map.ngm
.............\......\top_map.ncd
.............\......\top_map.mrp
.............\......\top_map.xrpt
.............\......\top.par
.............\......\top.ptwx
.............\......\top_pad.csv
.............\......\top.pad
.............\......\top_pad.txt
.............\......\top.unroutes
.............\......\top.ncd
.............\......\top.xpi
.............\......\top_par.xrpt
.............\......\top_guide.ncd
.............\......\top.twx
.............\......\top.twr
.............\......\netgen\synthesis\top_synthesis.nlf
.............\......\......\.........\top_synthesis.v
.............\......\top_envsettings.html
.............\......\top.bgn
.............\......\top.drc
.............\......\top.bit
.............\......\top_bitgen.xwbt
.............\......\top_usage.xml
.............\......\top_summary.xml
.............\......\usage_statistics_webtalk.html
.............\......\webtalk.log
.............\......\KKKK.cpj
.............\....Out\automake.log
.............\.......\bitgen.ut
.............\.......\coregen.log
.............\.......\coregen.prj
.............\.......\FPGA.dhp
.............\.......\prom.mcs
.............\.......\prom.prm
.............\.......\prom.sig
.............\.......\top.cmd_log
.............\.......\top.ll
.............\.......\top.mrp
.............\.......\top.msd
.............\.......\top.msk