文件名称:16QAM_verilog

  • 所属分类:
  • Modem编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 732kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • f*
  • 相关连接:
  • 下载说明:
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使用Verilog实现全数字的16QAM调制器,假设载波的频率为1MHz,数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
相关搜索: verilog16QAM

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下载文件列表

16QAM调制的Verilog实现\qam16_right_prj\ddsqam.asy

......................\...............\ddsqam.edn

......................\...............\ddsqam.sym

......................\...............\ddsqam.v

......................\...............\ddsqam.veo

......................\...............\ddsqam.vhd

......................\...............\ddsqam.vho

......................\...............\ddsqam.xco

......................\...............\ddsqam_flist.txt

......................\...............\ddsqam_readme.txt

......................\...............\ddsqam_SINCOS_TABLE_TRIG_ROM.mif

......................\...............\ddsqam_xmdf.tcl

......................\...............\qam16.v

......................\...............\qam16_right_prj.ise

......................\...............\qam16_right_prj.restore

......................\...............\qam16_summary.html

......................\...............\qam16_tb.fdo

......................\...............\qam16_tb.udo

......................\...............\qam16_tb.v

......................\...............\qam16_tb_wave.fdo

......................\...............\templates\coregen.xml

......................\...............\transcript

......................\...............\vsim.wlf

......................\...............\wave.do

......................\...............\.ork\ddsqam\verilog.asm

......................\...............\....\......\verilog.rw

......................\...............\....\......\_primary.dat

......................\...............\....\......\_primary.dbs

......................\...............\....\......\_primary.vhd

......................\...............\....\glbl\verilog.asm

......................\...............\....\....\verilog.rw

......................\...............\....\....\_primary.dat

......................\...............\....\....\_primary.dbs

......................\...............\....\....\_primary.vhd

......................\...............\....\qam16\verilog.asm

......................\...............\....\.....\verilog.rw

......................\...............\....\.....\_primary.dat

......................\...............\....\.....\_primary.dbs

......................\...............\....\.....\_primary.vhd

......................\...............\....\....._tb\verilog.asm

......................\...............\....\........\verilog.rw

......................\...............\....\........\_primary.dat

......................\...............\....\........\_primary.dbs

......................\...............\....\........\_primary.vhd

......................\...............\....\_info

......................\...............\....\_vmake

......................\...............\qam16_right_prj_xdb\tmp

......................\...............\tmp\_cg

......................\...............\work\ddsqam

......................\...............\....\glbl

......................\...............\....\qam16

......................\...............\....\qam16_tb

......................\...............\....\_temp

......................\...............\qam16_right_prj_xdb

......................\...............\templates

......................\...............\tmp

......................\...............\work

......................\...............\_xmsgs

......................\qam16_right_prj

16QAM调制的Verilog实现

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