文件名称:LCD
介绍说明－－下载内容均来自于网络，请自行研究使用
LCD驱动器的完整代码，详细verilog编程-LCD drive complete code, verilog detailed programming
(系统自动生成,下载前可以参看下载内容)
下载文件列表
LCD实验\Project\LCD_1602\constraint\LCD_Top.pdc
.......\.......\........\designer\impl1\designer.log
.......\.......\........\........\.....\LCD_Driver.ide_des
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\........dtf\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.plk
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\........\.....\........fp\LCD_Top.log
.......\.......\........\........\.....\..........\LCD_Top.pro
.......\.......\........\........\.....\PLL_1M.ide_des
.......\.......\........\hdl\Clock_Gen.v
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\simulation\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\.martgen\PLL_1M\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\.timulus\BtimErrors.log
.......\.......\........\........\LCD_Top.dsk
.......\.......\........\........\LCD_Top.hpj
.......\.......\........\........\waveperl.log
.......\.......\........\.ynthesis\.recordref
.......\.......\........\.........\designer\convert.log
.......\.......\........\.........\........\convert.tcl
.......\.......\........\.........\........\impl1\impl.prj_des
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\LCD_Top_syn.prj.convert.sav
.......\.......\........\.........\simulation\modelsim.ini
.......\.......\........\.........\..........\modelsim.ini.sav
.......\.......\........\.........\stdout.log
.......\.......\........\.........\.yntmp\LCD_Top.msg
.......\.......\........\.........\......\LCD_Top.plg
.......\.......\........\.........\......\LCD_Top_flink.htm
.......\.......\........\.........\......\LCD_Top_srr.htm
.......\.......\........\.........\......\LCD_Top_toc.htm
.......\.......\........\.........\......\sap.log
.......\.......\........\.........\traplog.tlg
.......\.......\........\.........\viewdraw\vf\project.lst
.......\.......\........\.........\........\viewdraw.ini
.......\.......\........\synthesis.zip
.......\.......\........\viewdraw\vf\project.lst
.......\.......\........\........\viewdraw.ini
.......\.......\LCD_1602.zip
.......\Source File\Clock_Gen.v
.......\...........\LCD_Driver.v
.......\...........\LCD_Top.v
.......\Project\LCD_1602\synthesis\designer\impl1\simulation
.......\.......\........\.........\........\....2\simulation
.......\.......\........\designer\impl1\LCD_Top.dtf
.......\.......\........\........\.....\LCD_Top_fp
.......\.......\........\........\.....\simulation
.......\.......\........\synthesis\designer\impl1
.......\.......\........\.........\........\impl2
.......\.......\........\.........\viewdraw\sch
.......\.......\........\.........\........\sym
.......\.......\........\.........\........\vf
.......\.......\........\.........\........\wir
.......\......
.......\.......\........\designer\impl1\designer.log
.......\.......\........\........\.....\LCD_Driver.ide_des
.......\.......\........\........\.....\LCD_Top.adb
.......\.......\........\........\.....\........dtf\verify.log
.......\.......\........\........\.....\LCD_Top.ide_des
.......\.......\........\........\.....\LCD_Top.pdb
.......\.......\........\........\.....\LCD_Top.pdb.depends
.......\.......\........\........\.....\LCD_Top.plk
.......\.......\........\........\.....\LCD_Top.tcl
.......\.......\........\........\.....\LCD_Top_ba.sdf
.......\.......\........\........\.....\LCD_Top_ba.v
.......\.......\........\........\.....\........fp\LCD_Top.log
.......\.......\........\........\.....\..........\LCD_Top.pro
.......\.......\........\........\.....\PLL_1M.ide_des
.......\.......\........\hdl\Clock_Gen.v
.......\.......\........\...\LCD_Driver.v
.......\.......\........\...\LCD_Top.v
.......\.......\........\LCD_1602.prj
.......\.......\........\simulation\meminit.dat
.......\.......\........\..........\modelsim.ini
.......\.......\........\..........\modelsim.ini.sav
.......\.......\........\.martgen\PLL_1M\PLL_1M.cxf
.......\.......\........\........\......\PLL_1M.gen
.......\.......\........\........\......\PLL_1M.log
.......\.......\........\........\......\PLL_1M.v
.......\.......\........\........\PLL_1M_work.ixf
.......\.......\........\........\smartgen.aws
.......\.......\........\.timulus\BtimErrors.log
.......\.......\........\........\LCD_Top.dsk
.......\.......\........\........\LCD_Top.hpj
.......\.......\........\........\waveperl.log
.......\.......\........\.ynthesis\.recordref
.......\.......\........\.........\designer\convert.log
.......\.......\........\.........\........\convert.tcl
.......\.......\........\.........\........\impl1\impl.prj_des
.......\.......\........\.........\LCD_Top.areasrr
.......\.......\........\.........\LCD_Top.edn
.......\.......\........\.........\LCD_Top.fse
.......\.......\........\.........\LCD_Top.htm
.......\.......\........\.........\LCD_Top.map
.......\.......\........\.........\LCD_Top.sap
.......\.......\........\.........\LCD_Top.sdf
.......\.......\........\.........\LCD_Top.srd
.......\.......\........\.........\LCD_Top.srm
.......\.......\........\.........\LCD_Top.srr
.......\.......\........\.........\LCD_Top.srs
.......\.......\........\.........\LCD_Top.tlg
.......\.......\........\.........\LCD_Top_sdc.sdc
.......\.......\........\.........\LCD_Top_syn.prj
.......\.......\........\.........\LCD_Top_syn.prj.convert.sav
.......\.......\........\.........\simulation\modelsim.ini
.......\.......\........\.........\..........\modelsim.ini.sav
.......\.......\........\.........\stdout.log
.......\.......\........\.........\.yntmp\LCD_Top.msg
.......\.......\........\.........\......\LCD_Top.plg
.......\.......\........\.........\......\LCD_Top_flink.htm
.......\.......\........\.........\......\LCD_Top_srr.htm
.......\.......\........\.........\......\LCD_Top_toc.htm
.......\.......\........\.........\......\sap.log
.......\.......\........\.........\traplog.tlg
.......\.......\........\.........\viewdraw\vf\project.lst
.......\.......\........\.........\........\viewdraw.ini
.......\.......\........\synthesis.zip
.......\.......\........\viewdraw\vf\project.lst
.......\.......\........\........\viewdraw.ini
.......\.......\LCD_1602.zip
.......\Source File\Clock_Gen.v
.......\...........\LCD_Driver.v
.......\...........\LCD_Top.v
.......\Project\LCD_1602\synthesis\designer\impl1\simulation
.......\.......\........\.........\........\....2\simulation
.......\.......\........\designer\impl1\LCD_Top.dtf
.......\.......\........\........\.....\LCD_Top_fp
.......\.......\........\........\.....\simulation
.......\.......\........\synthesis\designer\impl1
.......\.......\........\.........\........\impl2
.......\.......\........\.........\viewdraw\sch
.......\.......\........\.........\........\sym
.......\.......\........\.........\........\vf
.......\.......\........\.........\........\wir
.......\......