文件名称:add4
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四位加法器verilog源代码，经过modelsim仿真验证正确，用ISE7.1i以上版本打开工程文件。-Four adder verilog source code, right after the modelsim simulation with ISE7.1i later open the project file.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
add4
....\__projnav
....\.........\add4.gfl
....\.........\add4.xst
....\.........\add4_flowplus.gfl
....\.........\full_add1.xst
....\.........\runXst_tcl.rsp
....\.........\sumrpt_tcl.rsp
....\__projnav.log
....\_xmsgs
....\add4.cmd_log
....\add4.dhp
....\add4.ise
....\add4.ise_ISE_Backup
....\add4.lso
....\add4.ngc
....\add4.ngr
....\add4.prj
....\add4.stx
....\add4.syr
....\add4_summary.html
....\add4_tbw.ant
....\add4_tbw.fdo
....\add4_tbw.tbw
....\add4_tbw.tfw
....\add4_tbw.udo
....\add4_tbw.xwv
....\add4_tbw.xwv_bak
....\add4_tbw_bencher.prj
....\add4_vhdl.prj
....\adder4.v
....\automake.log
....\full_add1.cmd_log
....\full_add1.lso
....\full_add1.ngc
....\full_add1.ngr
....\full_add1.prj
....\full_add1.stx
....\full_add1.syr
....\full_add1.v
....\full_add1_summary.html
....\full_add1_vhdl.prj
....\results.txt
....\transcript
....\vsim.wlf
....\work
....\....\_info
....\....\_opt
....\....\....\_deps
....\....\....\e__Xilinx_verilog_mti_se_XilinxCoreLib_ver__info
....\....\....\e__Xilinx_verilog_mti_se_unisims_ver__info
....\....\....\work__info
....\....\....\work_add4_fast.dt2
....\....\....\work_add4_tbw_fast.asm
....\....\....\work_add4_tbw_fast.dt2
....\....\....\work_full_add1_fast.dt2
....\....\....\work_glbl_fast.asm
....\....\....\work_glbl_fast.dt2
....\....\_temp
....\....\add4
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\add4_tbw
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\full_add1
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\.........\verilog.asm
....\....\glbl
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\xst
....\...\dump.xst
....\...\........\add4.prj
....\...\........\........\ngx
....\...\........\........\...\notopt
....\...\........\........\...\opt
....\...\........\full_add1.prj
....\...\........\.............\ngx
....\...\........\.............\...\notopt
....\...\........\.............\...\opt
....\...\work
....\...\....\hdllib.ref
....\...\....\vlg14
....\...\....\.....\full__add1.bin
....\...\....\vlg49
....\...\....\.....\add4.bin
....\__projnav
....\.........\add4.gfl
....\.........\add4.xst
....\.........\add4_flowplus.gfl
....\.........\full_add1.xst
....\.........\runXst_tcl.rsp
....\.........\sumrpt_tcl.rsp
....\__projnav.log
....\_xmsgs
....\add4.cmd_log
....\add4.dhp
....\add4.ise
....\add4.ise_ISE_Backup
....\add4.lso
....\add4.ngc
....\add4.ngr
....\add4.prj
....\add4.stx
....\add4.syr
....\add4_summary.html
....\add4_tbw.ant
....\add4_tbw.fdo
....\add4_tbw.tbw
....\add4_tbw.tfw
....\add4_tbw.udo
....\add4_tbw.xwv
....\add4_tbw.xwv_bak
....\add4_tbw_bencher.prj
....\add4_vhdl.prj
....\adder4.v
....\automake.log
....\full_add1.cmd_log
....\full_add1.lso
....\full_add1.ngc
....\full_add1.ngr
....\full_add1.prj
....\full_add1.stx
....\full_add1.syr
....\full_add1.v
....\full_add1_summary.html
....\full_add1_vhdl.prj
....\results.txt
....\transcript
....\vsim.wlf
....\work
....\....\_info
....\....\_opt
....\....\....\_deps
....\....\....\e__Xilinx_verilog_mti_se_XilinxCoreLib_ver__info
....\....\....\e__Xilinx_verilog_mti_se_unisims_ver__info
....\....\....\work__info
....\....\....\work_add4_fast.dt2
....\....\....\work_add4_tbw_fast.asm
....\....\....\work_add4_tbw_fast.dt2
....\....\....\work_full_add1_fast.dt2
....\....\....\work_glbl_fast.asm
....\....\....\work_glbl_fast.dt2
....\....\_temp
....\....\add4
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\add4_tbw
....\....\........\_primary.dat
....\....\........\_primary.vhd
....\....\........\verilog.asm
....\....\full_add1
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\.........\verilog.asm
....\....\glbl
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\xst
....\...\dump.xst
....\...\........\add4.prj
....\...\........\........\ngx
....\...\........\........\...\notopt
....\...\........\........\...\opt
....\...\........\full_add1.prj
....\...\........\.............\ngx
....\...\........\.............\...\notopt
....\...\........\.............\...\opt
....\...\work
....\...\....\hdllib.ref
....\...\....\vlg14
....\...\....\.....\full__add1.bin
....\...\....\vlg49
....\...\....\.....\add4.bin