文件名称:fpga_pc
介绍说明－－下载内容均来自于网络，请自行研究使用
该源码实现了XILINX的FPGA(Spartan 3E)与计算机的通信，用到了rs232串口、ps/2键盘接口、lcd液晶，是学习FPGA很好的资料-The source implementation of the XILINX' s FPGA (Spartan 3E) and computer communications, use the rs232 serial port, ps/2 keyboard interface, lcd LCD is good information to learn FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fpga_pc\fpga_pc_ngdbuild.xrpt
.......\........xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\GuiProjectData
.......\...........\...\...\............\...................\GuiProjectData_StrTbl
.......\...........\...\...\............\................\dpm_project_main\dpm_project_main
.......\...........\...\...\............\................\................\dpm_project_main_StrTbl
.......\...........\...\...\............\................\................\NameMap
.......\...........\...\...\............\................\................\NameMap_StrTbl
.......\...........\...\...\............\................\__stored_objects__
.......\...........\...\...\............\................\__stored_objects___StrTbl
.......\...........\...\...\............\................\__stored_object_table__
.......\...........\...\...\............\HierarchicalDesign\HDProject\HDProject
.......\...........\...\...\............\..................\.........\HDProject_StrTbl
.......\...........\...\...\............\..................\__stored_object_table__
.......\...........\...\...\..REGISTRY__\Autonym\regkeys
.......\...........\...\...\............\HierarchicalDesign\HDProject\regkeys
.......\...........\...\...\............\..................\regkeys
.......\...........\...\...\............\ProjectNavigator\regkeys
.......\...........\...\...\............\................Gui\regkeys
.......\...........\...\...\............\STE\regkeys
.......\...........\...\...\............\...\xst\regkeys
.......\...........\...\...\............\...\ngdbuild\regkeys
.......\...........\...\...\............\...\map\regkeys
.......\...........\...\...\............\...\par\regkeys
.......\...........\...\...\............\...\trce\regkeys
.......\...........\...\...\............\...\bitgen\regkeys
.......\...........\...\...\............\.rcCtrl\regkeys
.......\...........\...\...\............\WebTalk\DesignDataCollection\regkeys
.......\...........\...\...\............\.......\regkeys
.......\...........\...\...\............\_ProjRepoInternal_\regkeys
.......\...........\...\...\............\common\regkeys
.......\...........\...\...\version
.......\...........\...\ise.lock
.......\...........\cst.xbcd
.......\fpga_pc.ngd
.......\fpga_pc_prev_built.ngd
.......\_xmsgs\xst.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\map.xmsgs
.......\......\par.xmsgs
.......\......\trce.xmsgs
.......\......\bitgen.xmsgs
.......\fpga_pc.ise
.......\fpga_pc.restore
.......\fpga_pc_map.mrp
.......\fpga_pc.v
.......\fpga_pc_map.map
.......\fpga_pc.pcf
.......\ps2scan.v
.......\fpga_pc_map.ngm
.......\fpga_pc.par
.......\speed_select.v
.......\fpga_pc_map.ncd
.......\fpga_pc.ncd
.......\.lso
.......\fpga_pc_usage.xml
.......\fpga_pc_summary.xml
.......\fpga_pc_map.xrpt
.......\fpga_pc_par.xrpt
.......\fpga_pc.xpi
.......\fpga_pc.prj
.......\xst\work\vlg20\speed__select.bin
.......\...\....\...76\ps2scan.bin
.......\...\....\...38\my__uart__tx.bin
.......\...\....\...74\fpga__pc.bin
.......\...\....\hdllib.ref
.......\...\....\vlg5F\lcd.bin
.......\...\....\...21\uart__rx.bin
.......\...\....\....B\uart__tx.bin
.......\...\dump.xst\fpga_pc.prj\ntrc.scr
.......\fpga_pc.xst
.......\fpga_pc.pad
.......\fpga_pc.stx
.......\fpga_pc.ptwx
.......\fpga_pc.bld
.......\fpga_pc_pad.csv
.......\fpga_pc.twx
.......\fpga_pc.twr
.......\fpga_pc.bgn
.......\fpga_pc.ucf
.......\fpga_pc.ut
.......\fpga_pc.lfp
.......\_pace.ucf
.......\fpga_pc_pad.txt
.......\fpga_pc.unroutes
.......\fpga_pc.cmd_log
.......\fpga_pc_guide.ncd
.......\fpga_pc.drc
.......\fpga_pc.bit
.......\fpga_pc.syr
.......\_impact.cmd
.......\device_usage_statistics.html
.......\fpga_pc_summary.html
.......\lcd.v
.......\fpga_pc_xst.xrpt
.......\_impact.log
.......\fpga_pc.lso
.......\fpga_pc.ntrc_log
.......\fpga_pc.ngr
.......\fpga_pc.ngc
.......\test.txt
.......\........xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\GuiProjectData
.......\...........\...\...\............\...................\GuiProjectData_StrTbl
.......\...........\...\...\............\................\dpm_project_main\dpm_project_main
.......\...........\...\...\............\................\................\dpm_project_main_StrTbl
.......\...........\...\...\............\................\................\NameMap
.......\...........\...\...\............\................\................\NameMap_StrTbl
.......\...........\...\...\............\................\__stored_objects__
.......\...........\...\...\............\................\__stored_objects___StrTbl
.......\...........\...\...\............\................\__stored_object_table__
.......\...........\...\...\............\HierarchicalDesign\HDProject\HDProject
.......\...........\...\...\............\..................\.........\HDProject_StrTbl
.......\...........\...\...\............\..................\__stored_object_table__
.......\...........\...\...\..REGISTRY__\Autonym\regkeys
.......\...........\...\...\............\HierarchicalDesign\HDProject\regkeys
.......\...........\...\...\............\..................\regkeys
.......\...........\...\...\............\ProjectNavigator\regkeys
.......\...........\...\...\............\................Gui\regkeys
.......\...........\...\...\............\STE\regkeys
.......\...........\...\...\............\...\xst\regkeys
.......\...........\...\...\............\...\ngdbuild\regkeys
.......\...........\...\...\............\...\map\regkeys
.......\...........\...\...\............\...\par\regkeys
.......\...........\...\...\............\...\trce\regkeys
.......\...........\...\...\............\...\bitgen\regkeys
.......\...........\...\...\............\.rcCtrl\regkeys
.......\...........\...\...\............\WebTalk\DesignDataCollection\regkeys
.......\...........\...\...\............\.......\regkeys
.......\...........\...\...\............\_ProjRepoInternal_\regkeys
.......\...........\...\...\............\common\regkeys
.......\...........\...\...\version
.......\...........\...\ise.lock
.......\...........\cst.xbcd
.......\fpga_pc.ngd
.......\fpga_pc_prev_built.ngd
.......\_xmsgs\xst.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\map.xmsgs
.......\......\par.xmsgs
.......\......\trce.xmsgs
.......\......\bitgen.xmsgs
.......\fpga_pc.ise
.......\fpga_pc.restore
.......\fpga_pc_map.mrp
.......\fpga_pc.v
.......\fpga_pc_map.map
.......\fpga_pc.pcf
.......\ps2scan.v
.......\fpga_pc_map.ngm
.......\fpga_pc.par
.......\speed_select.v
.......\fpga_pc_map.ncd
.......\fpga_pc.ncd
.......\.lso
.......\fpga_pc_usage.xml
.......\fpga_pc_summary.xml
.......\fpga_pc_map.xrpt
.......\fpga_pc_par.xrpt
.......\fpga_pc.xpi
.......\fpga_pc.prj
.......\xst\work\vlg20\speed__select.bin
.......\...\....\...76\ps2scan.bin
.......\...\....\...38\my__uart__tx.bin
.......\...\....\...74\fpga__pc.bin
.......\...\....\hdllib.ref
.......\...\....\vlg5F\lcd.bin
.......\...\....\...21\uart__rx.bin
.......\...\....\....B\uart__tx.bin
.......\...\dump.xst\fpga_pc.prj\ntrc.scr
.......\fpga_pc.xst
.......\fpga_pc.pad
.......\fpga_pc.stx
.......\fpga_pc.ptwx
.......\fpga_pc.bld
.......\fpga_pc_pad.csv
.......\fpga_pc.twx
.......\fpga_pc.twr
.......\fpga_pc.bgn
.......\fpga_pc.ucf
.......\fpga_pc.ut
.......\fpga_pc.lfp
.......\_pace.ucf
.......\fpga_pc_pad.txt
.......\fpga_pc.unroutes
.......\fpga_pc.cmd_log
.......\fpga_pc_guide.ncd
.......\fpga_pc.drc
.......\fpga_pc.bit
.......\fpga_pc.syr
.......\_impact.cmd
.......\device_usage_statistics.html
.......\fpga_pc_summary.html
.......\lcd.v
.......\fpga_pc_xst.xrpt
.......\_impact.log
.......\fpga_pc.lso
.......\fpga_pc.ntrc_log
.......\fpga_pc.ngr
.......\fpga_pc.ngc
.......\test.txt