文件名称:ex15_logic_analysis

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 5.63mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 樊**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

逻辑分析仪用FPGA实现,基于Verilog HDL的程序实现-Logic analyzer using FPGA, Verilog HDL-based programs to achieve
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ex15_logic_analysis\logic_analysis\char_rom.bsf

...................\..............\char_rom.qip

...................\..............\char_rom.v

...................\..............\char_rom_bb.v

...................\..............\char_rom_data.mif

...................\..............\char_rom_data.rar

...................\..............\char_rom_inst.v

...................\..............\char_rom_wave0.jpg

...................\..............\char_rom_waveforms.html

...................\..............\Ch_rom.qip

...................\..............\db\altsyncram_0e71.tdf

...................\..............\..\altsyncram_5m31.tdf

...................\..............\..\altsyncram_dg61.tdf

...................\..............\..\altsyncram_fc61.tdf

...................\..............\..\altsyncram_hd51.tdf

...................\..............\..\altsyncram_lp51.tdf

...................\..............\..\altsyncram_n0a1.tdf

...................\..............\..\altsyncram_op51.tdf

...................\..............\..\altsyncram_ql51.tdf

...................\..............\..\altsyncram_u0a1.tdf

...................\..............\..\cntr_0df.tdf

...................\..............\..\logic_analysis.asm.qmsg

...................\..............\..\logic_analysis.cbx.xml

...................\..............\..\logic_analysis.cmp.bpm

...................\..............\..\logic_analysis.cmp.cdb

...................\..............\..\logic_analysis.cmp.ecobp

...................\..............\..\logic_analysis.cmp.hdb

...................\..............\..\logic_analysis.cmp.kpt

...................\..............\..\logic_analysis.cmp.logdb

...................\..............\..\logic_analysis.cmp.rdb

...................\..............\..\logic_analysis.cmp0.ddb

...................\..............\..\logic_analysis.cmp_merge.kpt

...................\..............\..\logic_analysis.db_info

...................\..............\..\logic_analysis.eco.cdb

...................\..............\..\logic_analysis.eda.qmsg

...................\..............\..\logic_analysis.fit.qmsg

...................\..............\..\logic_analysis.hier_info

...................\..............\..\logic_analysis.hif

...................\..............\..\logic_analysis.lpc.html

...................\..............\..\logic_analysis.lpc.rdb

...................\..............\..\logic_analysis.lpc.txt

...................\..............\..\logic_analysis.map.bpm

...................\..............\..\logic_analysis.map.cdb

...................\..............\..\logic_analysis.map.ecobp

...................\..............\..\logic_analysis.map.hdb

...................\..............\..\logic_analysis.map.kpt

...................\..............\..\logic_analysis.map.logdb

...................\..............\..\logic_analysis.map.qmsg

...................\..............\..\logic_analysis.map_bb.cdb

...................\..............\..\logic_analysis.map_bb.hdb

...................\..............\..\logic_analysis.map_bb.logdb

...................\..............\..\logic_analysis.pre_map.cdb

...................\..............\..\logic_analysis.pre_map.hdb

...................\..............\..\logic_analysis.rpp.qmsg

...................\..............\..\logic_analysis.rtlv.hdb

...................\..............\..\logic_analysis.rtlv_sg.cdb

...................\..............\..\logic_analysis.rtlv_sg_swap.cdb

...................\..............\..\logic_analysis.sgate.rvd

...................\..............\..\logic_analysis.sgate_sm.rvd

...................\..............\..\logic_analysis.sgdiff.cdb

...................\..............\..\logic_analysis.sgdiff.hdb

...................\..............\..\logic_analysis.sld_design_entry.sci

...................\..............\..\logic_analysis.sld_design_entry_dsc.sci

...................\..............\..\logic_analysis.sta.qmsg

...................\..............\..\logic_analysis.sta.rdb

...................\..............\..\logic_analysis.sta_cmp.8_slow.tdb

...................\..............\..\logic_analysis.syn_hier_info

...................\..............\..\l

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