文件名称:FFT

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.99mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • g**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

使用内嵌M3核的FPGA实现FFT的开发-embed the M3 s FPGA for FFT
(系统自动生成,下载前可以参看下载内容)

下载文件列表

FFT\FFT\smartgen\smartgen.aws

...\...\hdl\actar.v

...\...\...\actar.cxf

...\...\...\actram.v

...\...\...\actram.cxf

...\...\...\fftDp.v

...\...\...\fftHeader.v

...\...\...\fftSm.v

...\...\...\fftTop.v

...\...\...\twiddle.v

...\...\viewdraw\viewdraw.ini

...\...\........\.f\project.lst

...\...\simulation\modelsim.ini

...\...\.ynthesis\stdout.log

...\...\.........\.yntmp\fftTop_flink.htm

...\...\.........\......\fftTop_srr.htm

...\...\.........\......\fftTop_toc.htm

...\...\.........\......\fftTop.msg

...\...\.........\......\sap.log

...\...\.........\......\fftTop.plg

...\...\.........\......\sap_log_flink.htm

...\...\.........\......\sap_log_srr.htm

...\...\.........\......\fftTop_1_flink.htm

...\...\.........\......\fftTop_1.msg

...\...\.........\......\fftTop_1_srr.htm

...\...\.........\......\fftTop_1_toc.htm

...\...\.........\......\fftTop_1.plg

...\...\.........\......\sap_log_toc.htm

...\...\.........\backup\fftTop.srr

...\...\.........\......\fftTop_1.srr

...\...\.........\run_options.txt

...\...\.........\scratchproject.prs

...\...\.........\fftTop.tlg

...\...\.........\fftTop.so

...\...\.........\fftTop.htm

...\...\.........\fftTop.srl

...\...\.........\fftTop.sap

...\...\.........\fftTop.fse

...\...\.........\fftTop.szr

...\...\.........\traplog.tlg

...\...\.........\.recordref_modgen

...\...\.........\fftTop.srd

...\...\.........\fftTop.srm

...\...\.........\fftTop.map

...\...\.........\fftTop.edn

...\...\.........\fftTop.sdf

...\...\.........\fftTop.pdc

...\...\.........\fftTop_sdc.sdc

...\...\.........\fftTop.areasrr

...\...\.........\fftTop_syn.prd

...\...\.........\fftTop_drc.rpt

...\...\.........\fftTop.srr

...\...\.........\fftTop.srs

...\...\.........\fftTop_1.tlg

...\...\.........\fftTop_1.srl

...\...\.........\fftTop_1.htm

...\...\.........\fftTop_1.sap

...\...\.........\fftTop_1.fse

...\...\.........\fftTop_1.szr

...\...\.........\fftTop_1.srd

...\...\.........\fftTop_1.srm

...\...\.........\fftTop_1.map

...\...\.........\fftTop_1.edn

...\...\.........\fftTop_1.sdf

...\...\.........\fftTop_1.pdc

...\...\.........\fftTop_1_sdc.sdc

...\...\.........\fftTop_1.so

...\...\.........\fftTop_1.areasrr

...\...\.........\sap_log.htm

...\...\.........\fftTop_syn.prj

...\...\.........\fftTop_1.srr

...\...\.........\identify.log

...\...\.........\fftTop_1.srs

...\...\designer\impl1\fftTop.ide_des

...\...\........\.....\sm_top.ide_des

...\...\........\.....\fftTop.tcl

...\...\........\.....\designer_synth_check.log

...\...\........\.....\autoScale.ide_des

...\...\........\.....\edgeDetect.ide_des

...\...\........\.....\fftTop_1.ide_des

...\...\FFT.prj

...\...\designer\impl1\simulation

...\...\viewdraw\vf

...\...\........\sch

...\...\........\sym

...\...\........\wir

...\...\synthesis\syntmp

...\...\.........\coreip

...\...\.........\xplace

...\...\.........\backup

...\...\designer\impl1

...\...\smartgen

...\...\hdl

...\...\constraint

...\...\viewdraw

...\...\component

...\...\coreconsole

...\...\simulation

...\...\synthesis

...\...\phy_synthesis

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