文件名称:12
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4位除法器
library IEEE
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
entity fpdiv is
port (
DIVz: out STD_LOGIC
A: in STD_LOGIC_VECTOR (3 downto 0)
B: in STD_LOGIC_VECTOR (3 downto 0)
data_out: out STD_LOGIC_VECTOR (3 downto 0)
)
end fpdiv -4-bit divider library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port (DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LOGIC_VECTOR (3 downto 0)) end fpdiv
library IEEE
use IEEE.std_logic_1164.all
use IEEE.std_logic_unsigned.all
entity fpdiv is
port (
DIVz: out STD_LOGIC
A: in STD_LOGIC_VECTOR (3 downto 0)
B: in STD_LOGIC_VECTOR (3 downto 0)
data_out: out STD_LOGIC_VECTOR (3 downto 0)
)
end fpdiv -4-bit divider library IEEE use IEEE.std_logic_1164.all use IEEE.std_logic_unsigned.all entity fpdiv is port (DIVz: out STD_LOGIC A: in STD_LOGIC_VECTOR (3 downto 0) B: in STD_LOGIC_VECTOR (3 downto 0) data_out: out STD_LOGIC_VECTOR (3 downto 0)) end fpdiv
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除法器.txt