文件名称:2
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使用变量的状态机
library ieee
use ieee.std_logic_1164.all
ENTITY fsm2 IS
PORT(clock,x : IN BIT z : OUT BIT)
END fsm2
-------------------------------------------------
ARCHITECTURE using_wait OF fsm2 IS
TYPE state_type IS (s0,s1,s2,s3)
BEGIN
PROCESS
VARIABLE state : state_type := s0
BEGIN
WAIT UNTIL (clock EVENT AND clock = 1 )
CASE state IS-Using the variable state machine library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT (clock, x: IN BIT z: OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0, s1, s2, s3) BEGIN PROCESS VARIABLE state: state_type: = s0 BEGIN WAIT UNTIL (clock' EVENT AND clock = ' 1 ' ) CASE state IS
library ieee
use ieee.std_logic_1164.all
ENTITY fsm2 IS
PORT(clock,x : IN BIT z : OUT BIT)
END fsm2
-------------------------------------------------
ARCHITECTURE using_wait OF fsm2 IS
TYPE state_type IS (s0,s1,s2,s3)
BEGIN
PROCESS
VARIABLE state : state_type := s0
BEGIN
WAIT UNTIL (clock EVENT AND clock = 1 )
CASE state IS-Using the variable state machine library ieee use ieee.std_logic_1164.all ENTITY fsm2 IS PORT (clock, x: IN BIT z: OUT BIT) END fsm2 ------------------------------------------------- ARCHITECTURE using_wait OF fsm2 IS TYPE state_type IS (s0, s1, s2, s3) BEGIN PROCESS VARIABLE state: state_type: = s0 BEGIN WAIT UNTIL (clock' EVENT AND clock = ' 1 ' ) CASE state IS
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