文件名称:vhdl
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4位乘法器 vhdl
library IEEE
use IEEE.std_logic_1164.all
entity one_bit_adder is
port (
A: in STD_LOGIC
B: in STD_LOGIC
C_in: in STD_LOGIC
S: out STD_LOGIC
C_out: out STD_LOGIC
)
end one_bit_adder -4-bit multiplier vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port (A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC) end one_bit_adder
library IEEE
use IEEE.std_logic_1164.all
entity one_bit_adder is
port (
A: in STD_LOGIC
B: in STD_LOGIC
C_in: in STD_LOGIC
S: out STD_LOGIC
C_out: out STD_LOGIC
)
end one_bit_adder -4-bit multiplier vhdl library IEEE use IEEE.std_logic_1164.all entity one_bit_adder is port (A: in STD_LOGIC B: in STD_LOGIC C_in: in STD_LOGIC S: out STD_LOGIC C_out: out STD_LOGIC) end one_bit_adder
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vhdl.txt