文件名称:ji-shu-qi
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fpga 本例程为加减法计数器，主要实现的加减法计数的功能-fpga counter the routine for the addition and subtraction, addition and subtraction to achieve the main function of count
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下载文件列表
example3\cmp_state.ini
........\counter.asm.rpt
........\counter.cdf
........\counter.done
........\counter.dpf
........\counter.fit.rpt
........\counter.fit.smsg
........\counter.fit.summary
........\counter.flow.rpt
........\counter.map.rpt
........\counter.map.summary
........\counter.pin
........\counter.pof
........\counter.qpf
........\counter.qsf
........\counter.qws
........\counter.tan.rpt
........\counter.tan.summary
........\counter.vhd
........\db\counter.db_info
........\..\counter.eco.cdb
........\..\counter.sld_design_entry.sci
........\实验说明.txt
........\db
example3
........\counter.asm.rpt
........\counter.cdf
........\counter.done
........\counter.dpf
........\counter.fit.rpt
........\counter.fit.smsg
........\counter.fit.summary
........\counter.flow.rpt
........\counter.map.rpt
........\counter.map.summary
........\counter.pin
........\counter.pof
........\counter.qpf
........\counter.qsf
........\counter.qws
........\counter.tan.rpt
........\counter.tan.summary
........\counter.vhd
........\db\counter.db_info
........\..\counter.eco.cdb
........\..\counter.sld_design_entry.sci
........\实验说明.txt
........\db
example3