文件名称:uart
介绍说明－－下载内容均来自于网络，请自行研究使用
232串口，我见过的最好的一个VERILOG描述的串口程序-232, one of the best I' ve ever seen descr iption of the serial program VERILOG
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart\UART设计文档.pdf
....\读我.txt
....\Mcu\UartTest\FpgaInc.h
....\...\........\main.c
....\...\........\stdinc.h
....\...\........\UartCtrl.c
....\...\........\UartCtrl.h
....\...\........\UartTest.dep
....\...\........\UartTest.ewd
....\...\........\UartTest.ewp
....\...\........\UartTest.eww
....\...\........\settings\test.cspy.bat
....\...\........\........\test.dbgdt
....\...\........\........\test.dni
....\...\........\........\test.wsdt
....\...\........\........\UartTest.cspy.bat
....\...\........\........\UartTest.dni
....\...\........\........\UartTest.wsdt
....\fpga\V0p10\top.bsf
....\....\.....\uart.asm.rpt
....\....\.....\uart.cdf
....\....\.....\uart.done
....\....\.....\uart.dpf
....\....\.....\uart.eda.rpt
....\....\.....\uart.fit.rpt
....\....\.....\uart.fit.smsg
....\....\.....\uart.fit.summary
....\....\.....\uart.flow.rpt
....\....\.....\uart.map.rpt
....\....\.....\uart.map.smsg
....\....\.....\uart.map.summary
....\....\.....\uart.pin
....\....\.....\uart.pof
....\....\.....\uart.qpf
....\....\.....\uart.qsf
....\....\.....\uart.qws
....\....\.....\uart.sof
....\....\.....\uart.tan.rpt
....\....\.....\uart.tan.summary
....\....\.....\uart_assignment_defaults.qdf
....\....\.....\uart_description.txt
....\....\.....\uart_nativelink_simulation.rpt
....\....\.....\testbench\ModelSim.jpg
....\....\.....\.........\tcl_stacktrace.txt
....\....\.....\.........\top_tb.v
....\....\.....\.........\transcript
....\....\.....\.........\uart.cr.mti
....\....\.....\.........\uart.mpf
....\....\.....\.........\vish_stacktrace.vstf
....\....\.....\.........\vsim.wlf
....\....\.....\.........\vsim_stacktrace.vstf
....\....\.....\.........\work\_info
....\....\.....\.........\....\uart\verilog.asm
....\....\.....\.........\....\....\_primary.dat
....\....\.....\.........\....\....\_primary.vhd
....\....\.....\.........\....\txd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\.op_tb\verilog.asm
....\....\.....\.........\....\......\_primary.dat
....\....\.....\.........\....\......\_primary.vhd
....\....\.....\.........\....\...\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\rxd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\ebi\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\division\verilog.asm
....\....\.....\.........\....\........\_primary.dat
....\....\.....\.........\....\........\_primary.vhd
....\....\.....\.........\....\....der\verilog.asm
....\....\.....\.........\....\.......\_primary.dat
....\....\.....\.........\....\.......\_primary.vhd
....\....\.....\.........\cycloneII_v\_info
....\....\.....\src\divider.v
....\....\.....\...\ebi.v
....\....\.....\...\rxd.v
....\....\.....\...\top.v
....\....\.....\...\txd.v
....\....\.....\...\uart.v
....\....\.....\.imulation\modelsim\modelsim.ini
....\....\.....\..........\........\msim_transcript
....\....\.....\..........\........\uart.sft
....\....\.....\..........\........\uart.vo
....\....\.....\..........\........\uart_modelsim.xrf
....\....\.....\..........\........\uart_run_msim_rtl_verilog.do
....\....\.....\..........\........\uart_run_msim_rtl_verilog.do.bak
....\....\.....\..........\........\uart_v.sdo
....\....\.....\..........\........\vsim.wlf
....\....\.....\..........\........\rtl_work\_info
....\....\.....\..........\........\........\_vmake
....\....\.....\..........\........\........\uart\verilog.prw
....\....\.....\..........\........\........\....\verilog.psm
....\....\.....\..........\........\........\....\_primary.dat
....\....\.....\..........\........\........\....\_primary.dbs
....\....\.....\..........\........\........\....\_primary.vhd
....\....\.....\..........\........\........\txd\verilog.prw
....\读我.txt
....\Mcu\UartTest\FpgaInc.h
....\...\........\main.c
....\...\........\stdinc.h
....\...\........\UartCtrl.c
....\...\........\UartCtrl.h
....\...\........\UartTest.dep
....\...\........\UartTest.ewd
....\...\........\UartTest.ewp
....\...\........\UartTest.eww
....\...\........\settings\test.cspy.bat
....\...\........\........\test.dbgdt
....\...\........\........\test.dni
....\...\........\........\test.wsdt
....\...\........\........\UartTest.cspy.bat
....\...\........\........\UartTest.dni
....\...\........\........\UartTest.wsdt
....\fpga\V0p10\top.bsf
....\....\.....\uart.asm.rpt
....\....\.....\uart.cdf
....\....\.....\uart.done
....\....\.....\uart.dpf
....\....\.....\uart.eda.rpt
....\....\.....\uart.fit.rpt
....\....\.....\uart.fit.smsg
....\....\.....\uart.fit.summary
....\....\.....\uart.flow.rpt
....\....\.....\uart.map.rpt
....\....\.....\uart.map.smsg
....\....\.....\uart.map.summary
....\....\.....\uart.pin
....\....\.....\uart.pof
....\....\.....\uart.qpf
....\....\.....\uart.qsf
....\....\.....\uart.qws
....\....\.....\uart.sof
....\....\.....\uart.tan.rpt
....\....\.....\uart.tan.summary
....\....\.....\uart_assignment_defaults.qdf
....\....\.....\uart_description.txt
....\....\.....\uart_nativelink_simulation.rpt
....\....\.....\testbench\ModelSim.jpg
....\....\.....\.........\tcl_stacktrace.txt
....\....\.....\.........\top_tb.v
....\....\.....\.........\transcript
....\....\.....\.........\uart.cr.mti
....\....\.....\.........\uart.mpf
....\....\.....\.........\vish_stacktrace.vstf
....\....\.....\.........\vsim.wlf
....\....\.....\.........\vsim_stacktrace.vstf
....\....\.....\.........\work\_info
....\....\.....\.........\....\uart\verilog.asm
....\....\.....\.........\....\....\_primary.dat
....\....\.....\.........\....\....\_primary.vhd
....\....\.....\.........\....\txd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\.op_tb\verilog.asm
....\....\.....\.........\....\......\_primary.dat
....\....\.....\.........\....\......\_primary.vhd
....\....\.....\.........\....\...\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\rxd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\ebi\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\division\verilog.asm
....\....\.....\.........\....\........\_primary.dat
....\....\.....\.........\....\........\_primary.vhd
....\....\.....\.........\....\....der\verilog.asm
....\....\.....\.........\....\.......\_primary.dat
....\....\.....\.........\....\.......\_primary.vhd
....\....\.....\.........\cycloneII_v\_info
....\....\.....\src\divider.v
....\....\.....\...\ebi.v
....\....\.....\...\rxd.v
....\....\.....\...\top.v
....\....\.....\...\txd.v
....\....\.....\...\uart.v
....\....\.....\.imulation\modelsim\modelsim.ini
....\....\.....\..........\........\msim_transcript
....\....\.....\..........\........\uart.sft
....\....\.....\..........\........\uart.vo
....\....\.....\..........\........\uart_modelsim.xrf
....\....\.....\..........\........\uart_run_msim_rtl_verilog.do
....\....\.....\..........\........\uart_run_msim_rtl_verilog.do.bak
....\....\.....\..........\........\uart_v.sdo
....\....\.....\..........\........\vsim.wlf
....\....\.....\..........\........\rtl_work\_info
....\....\.....\..........\........\........\_vmake
....\....\.....\..........\........\........\uart\verilog.prw
....\....\.....\..........\........\........\....\verilog.psm
....\....\.....\..........\........\........\....\_primary.dat
....\....\.....\..........\........\........\....\_primary.dbs
....\....\.....\..........\........\........\....\_primary.vhd
....\....\.....\..........\........\........\txd\verilog.prw