文件名称:cpu
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用Verilog语言编写的单周期cpu，实现的指令有
add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu, sltiu, blez, j.
add,addu,addi,addiu,sub,subu,clo,clz,xori,nor,slt,slti,sltu,sltiu,blez,j.-Verilog languages ??with single-cycle cpu, implementation instructions are add, addu, addi, addiu, sub, subu, clo, clz, xori, nor, slt, slti, sltu, sltiu, blez, j.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
新建文件夹\ALU.v
..........\ALUctr.v
..........\CPU.v
..........\CtrlUnit.v
..........\Extend.v
..........\InstMemory.v
..........\Mux2to1_32.v
..........\Mux2to1_5.v
..........\NPC.v
..........\PCCount.v
..........\Register.v
新建文件夹
..........\ALUctr.v
..........\CPU.v
..........\CtrlUnit.v
..........\Extend.v
..........\InstMemory.v
..........\Mux2to1_32.v
..........\Mux2to1_5.v
..........\NPC.v
..........\PCCount.v
..........\Register.v
新建文件夹