文件名称:VGA_char
介绍说明－－下载内容均来自于网络，请自行研究使用
Verilog语言描述的VGA显示实验，主要目的是在屏幕上显示不同的字符，Quartus 10 中编译通过。-Verilog language descr iption of the VGA display experiment, the main purpose is to display different characters on the screen, Quartus 10 in the compile.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA_char
........\VGA_char.asm.rpt
........\VGA_char.cdf
........\VGA_char.done
........\VGA_char.dpf
........\VGA_char.eda.rpt
........\VGA_char.fit.rpt
........\VGA_char.fit.smsg
........\VGA_char.fit.summary
........\VGA_char.flow.rpt
........\VGA_char.map.rpt
........\VGA_char.map.summary
........\VGA_char.pin
........\VGA_char.pof
........\VGA_char.qpf
........\VGA_char.qsf
........\VGA_char.qws
........\VGA_char.sof
........\VGA_char.tan.rpt
........\VGA_char.tan.summary
........\VGA_char.v
........\VGA_char.v.bak
........\VGA_char_nativelink_simulation.rpt
........\db
........\..\VGA_char.asm.qmsg
........\..\VGA_char.asm.rdb
........\..\VGA_char.cbx.xml
........\..\VGA_char.cmp.bpm
........\..\VGA_char.cmp.cdb
........\..\VGA_char.cmp.ecobp
........\..\VGA_char.cmp.hdb
........\..\VGA_char.cmp.kpt
........\..\VGA_char.cmp.logdb
........\..\VGA_char.cmp.rdb
........\..\VGA_char.cmp.tdb
........\..\VGA_char.cmp0.ddb
........\..\VGA_char.cmp_merge.kpt
........\..\VGA_char.db_info
........\..\VGA_char.eco.cdb
........\..\VGA_char.eda.qmsg
........\..\VGA_char.fit.qmsg
........\..\VGA_char.hier_info
........\..\VGA_char.hif
........\..\VGA_char.lpc.html
........\..\VGA_char.lpc.rdb
........\..\VGA_char.lpc.txt
........\..\VGA_char.map.bpm
........\..\VGA_char.map.cdb
........\..\VGA_char.map.ecobp
........\..\VGA_char.map.hdb
........\..\VGA_char.map.kpt
........\..\VGA_char.map.logdb
........\..\VGA_char.map.qmsg
........\..\VGA_char.map_bb.cdb
........\..\VGA_char.map_bb.hdb
........\..\VGA_char.map_bb.logdb
........\..\VGA_char.pre_map.cdb
........\..\VGA_char.pre_map.hdb
........\..\VGA_char.rtlv.hdb
........\..\VGA_char.rtlv_sg.cdb
........\..\VGA_char.rtlv_sg_swap.cdb
........\..\VGA_char.sgdiff.cdb
........\..\VGA_char.sgdiff.hdb
........\..\VGA_char.sld_design_entry.sci
........\..\VGA_char.sld_design_entry_dsc.sci
........\..\VGA_char.smart_action.txt
........\..\VGA_char.syn_hier_info
........\..\VGA_char.tan.qmsg
........\..\VGA_char.tis_db_list.ddb
........\..\VGA_char.tmw_info
........\..\logic_util_heursitic.dat
........\..\prev_cmp_VGA_char.eda.qmsg
........\..\prev_cmp_VGA_char.map.qmsg
........\..\prev_cmp_VGA_char.qmsg
........\incremental_db
........\..............\README
........\..............\compiled_partitions
........\..............\...................\VGA_char.root_partition.cmp.cdb
........\..............\...................\VGA_char.root_partition.cmp.dfp
........\..............\...................\VGA_char.root_partition.cmp.hdb
........\..............\...................\VGA_char.root_partition.cmp.kpt
........\..............\...................\VGA_char.root_partition.cmp.logdb
........\..............\...................\VGA_char.root_partition.cmp.rcfdb
........\..............\...................\VGA_char.root_partition.cmp.re.rcfdb
........\..............\...................\VGA_char.root_partition.map.cdb
........\..............\...................\VGA_char.root_partition.map.dpi
........\..............\...................\VGA_char.root_partition.map.hdb
........\..............\...................\VGA_char.root_partition.map.kpt
........\output_file.jic
........\output_file.map
........\simulation
........\..........\modelsim
........\..........\........\VGA_char.sft
........\..........\........\VGA_char.vo
........\..........\........\VGA_char.vt
........\..........\........\VGA_char.vt.bak
........\..........\........\VGA_char_modelsim.xrf
........\..........\........\VGA_char_run_msim_rtl_verilog.do
........\..........\........\VGA_char_v.sdo
........\..........\........\modelsim.ini
........\VGA_char.asm.rpt
........\VGA_char.cdf
........\VGA_char.done
........\VGA_char.dpf
........\VGA_char.eda.rpt
........\VGA_char.fit.rpt
........\VGA_char.fit.smsg
........\VGA_char.fit.summary
........\VGA_char.flow.rpt
........\VGA_char.map.rpt
........\VGA_char.map.summary
........\VGA_char.pin
........\VGA_char.pof
........\VGA_char.qpf
........\VGA_char.qsf
........\VGA_char.qws
........\VGA_char.sof
........\VGA_char.tan.rpt
........\VGA_char.tan.summary
........\VGA_char.v
........\VGA_char.v.bak
........\VGA_char_nativelink_simulation.rpt
........\db
........\..\VGA_char.asm.qmsg
........\..\VGA_char.asm.rdb
........\..\VGA_char.cbx.xml
........\..\VGA_char.cmp.bpm
........\..\VGA_char.cmp.cdb
........\..\VGA_char.cmp.ecobp
........\..\VGA_char.cmp.hdb
........\..\VGA_char.cmp.kpt
........\..\VGA_char.cmp.logdb
........\..\VGA_char.cmp.rdb
........\..\VGA_char.cmp.tdb
........\..\VGA_char.cmp0.ddb
........\..\VGA_char.cmp_merge.kpt
........\..\VGA_char.db_info
........\..\VGA_char.eco.cdb
........\..\VGA_char.eda.qmsg
........\..\VGA_char.fit.qmsg
........\..\VGA_char.hier_info
........\..\VGA_char.hif
........\..\VGA_char.lpc.html
........\..\VGA_char.lpc.rdb
........\..\VGA_char.lpc.txt
........\..\VGA_char.map.bpm
........\..\VGA_char.map.cdb
........\..\VGA_char.map.ecobp
........\..\VGA_char.map.hdb
........\..\VGA_char.map.kpt
........\..\VGA_char.map.logdb
........\..\VGA_char.map.qmsg
........\..\VGA_char.map_bb.cdb
........\..\VGA_char.map_bb.hdb
........\..\VGA_char.map_bb.logdb
........\..\VGA_char.pre_map.cdb
........\..\VGA_char.pre_map.hdb
........\..\VGA_char.rtlv.hdb
........\..\VGA_char.rtlv_sg.cdb
........\..\VGA_char.rtlv_sg_swap.cdb
........\..\VGA_char.sgdiff.cdb
........\..\VGA_char.sgdiff.hdb
........\..\VGA_char.sld_design_entry.sci
........\..\VGA_char.sld_design_entry_dsc.sci
........\..\VGA_char.smart_action.txt
........\..\VGA_char.syn_hier_info
........\..\VGA_char.tan.qmsg
........\..\VGA_char.tis_db_list.ddb
........\..\VGA_char.tmw_info
........\..\logic_util_heursitic.dat
........\..\prev_cmp_VGA_char.eda.qmsg
........\..\prev_cmp_VGA_char.map.qmsg
........\..\prev_cmp_VGA_char.qmsg
........\incremental_db
........\..............\README
........\..............\compiled_partitions
........\..............\...................\VGA_char.root_partition.cmp.cdb
........\..............\...................\VGA_char.root_partition.cmp.dfp
........\..............\...................\VGA_char.root_partition.cmp.hdb
........\..............\...................\VGA_char.root_partition.cmp.kpt
........\..............\...................\VGA_char.root_partition.cmp.logdb
........\..............\...................\VGA_char.root_partition.cmp.rcfdb
........\..............\...................\VGA_char.root_partition.cmp.re.rcfdb
........\..............\...................\VGA_char.root_partition.map.cdb
........\..............\...................\VGA_char.root_partition.map.dpi
........\..............\...................\VGA_char.root_partition.map.hdb
........\..............\...................\VGA_char.root_partition.map.kpt
........\output_file.jic
........\output_file.map
........\simulation
........\..........\modelsim
........\..........\........\VGA_char.sft
........\..........\........\VGA_char.vo
........\..........\........\VGA_char.vt
........\..........\........\VGA_char.vt.bak
........\..........\........\VGA_char_modelsim.xrf
........\..........\........\VGA_char_run_msim_rtl_verilog.do
........\..........\........\VGA_char_v.sdo
........\..........\........\modelsim.ini