文件名称:EDA

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [WORD]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.95mb
  • 下载次数:
  • 0次
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  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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设计与验证verilog hdl配套光盘-Supporting the design and verification of verilog hdl CD
(系统自动生成,下载前可以参看下载内容)

下载文件列表

《设计与验证verilog hdl》配套光盘\Example-2-1\HelloVlog.v

.................................\........3-1\FullAdd.v

.................................\...........\transcript

.................................\..........2\FullAdd.v

.................................\..........3\CRC10.v

.................................\........4-1\cnt.prd

.................................\...........\cnt.prj

.................................\...........\rev_1\cnt1.edf

.................................\...........\.....\cnt1.fse

.................................\...........\.....\cnt1.srm

.................................\...........\.....\cnt1.srr

.................................\...........\.....\cnt1.srs

.................................\...........\.....\cnt1.tlg

.................................\...........\.....\cnt2.edf

.................................\...........\.....\cnt2.fse

.................................\...........\.....\cnt2.srm

.................................\...........\.....\cnt2.srr

.................................\...........\.....\cnt2.srs

.................................\...........\.....\cnt2.tlg

.................................\...........\.....\cnt3.edf

.................................\...........\.....\cnt3.fse

.................................\...........\.....\cnt3.srm

.................................\...........\.....\cnt3.srr

.................................\...........\.....\cnt3.srs

.................................\...........\.....\cnt3.tlg

.................................\...........\.....\syntmp\cnt1.plg

.................................\...........\.....\......\cnt2.msg

.................................\...........\.....\......\cnt2.plg

.................................\...........\.....\......\cnt3.msg

.................................\...........\.....\......\cnt3.plg

.................................\...........\source\cnt1.v

.................................\...........\......\cnt2.v

.................................\...........\......\cnt3.v

.................................\...........\......\syntmp.msg

.................................\...........\示例说明.doc

.................................\...........0\bibus\bibus.prd

.................................\............\.....\bibus.prj

.................................\............\.....\bibus.v

.................................\............\.....\decode.v

.................................\............\.....\rev_1\bibus.fse

.................................\............\.....\.....\bibus.srd

.................................\............\.....\.....\bibus.srm

.................................\............\.....\.....\bibus.srr

.................................\............\.....\.....\bibus.srs

.................................\............\.....\.....\bibus.sxr

.................................\............\.....\.....\bibus.tcl

.................................\............\.....\.....\bibus.tlg

.................................\............\.....\.....\bibus.vqm

.................................\............\.....\.....\bibus.xrf

.................................\............\.....\.....\bibus_cons.tcl

.................................\............\.....\.....\bibus_rm.tcl

.................................\............\.....\.....\rpt_bibus.areasrr

.................................\............\.....\.....\rpt_bibus_areasrr.htm

.................................\............\.....\.....\syntmp\bibus.msg

.................................\............\.....\.....\......\bibus.plg

.................................\............\.....\.....\......\bibus_cons_ui.tcl

.................................\............\.....\.....\verif\bibus.vif

.................................\............\.....\syntmp.msg

.................................\............\complex_bibus\complex_bibus.prd

.................................\............\.............\complex_bibus.prj

.................................\............\.............\complex_bibus.v

.................................\............\.............\complex_bibus2.v

.................................\.

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