文件名称:VGA
介绍说明－－下载内容均来自于网络，请自行研究使用
改源码是采用VERILOG编写的驱动VGA显示屏的，能显示彩条和方格，是FPGA学习的好资料-Change the VERILOG source code is written using VGA display driver, and can display color bars and squares, is good information to learn FPGA
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA\Thumbs.db
...\参数设置.doc
...\vga_OK\pll1.prj
...\......\viewdraw\vf\project.lst
...\......\........\sym\newCore.1
...\......\........\viewdraw.ini
...\......\synthesis\.recordref_modgen
...\......\.........\run_options.txt
...\......\.........\scratchproject.prs
...\......\.........\stdout.log
...\......\.........\traplog.tlg
...\......\.........\vga.areasrr
...\......\.........\vga.edn
...\......\.........\vga.fse
...\......\.........\vga.htm
...\......\.........\vga.map
...\......\.........\vga.pdc
...\......\.........\vga.sap
...\......\.........\vga.sdf
...\......\.........\vga.so
...\......\.........\vga.srd
...\......\.........\vga.srl
...\......\.........\vga.srm
...\......\.........\vga.szr
...\......\.........\vga.tlg
...\......\.........\vga_sdc.sdc
...\......\.........\syntmp\sap.log
...\......\.........\......\sap_log_flink.htm
...\......\.........\......\sap_log_srr.htm
...\......\.........\......\vga.msg
...\......\.........\......\vga.plg
...\......\.........\......\vga_flink.htm
...\......\.........\......\vga_srr.htm
...\......\.........\......\vga_toc.htm
...\......\.........\backup\vga.srr
...\......\.........\vga_syn.prj
...\......\.........\vga.srr
...\......\.........\identify.log
...\......\.........\vga.srs
...\......\.martgen\newCore_work.ixf
...\......\........\.......\newCore.cxf
...\......\........\.......\newCore.gen
...\......\........\.......\newCore.log
...\......\........\.......\newCore.v
...\......\........\smartgen.aws
...\......\.imulation\modelsim.ini.sav
...\......\..........\modelsim.ini
...\......\hdl\vga.v.bak
...\......\...\vga.v
...\......\designer\impl1\designer.log
...\......\........\.....\newCore.ide_des
...\......\........\.....\vga.adb
...\......\........\.....\vga.ide_des
...\......\........\.....\vga.pdb
...\......\........\.....\vga.pdb.depends
...\......\........\.....\vga.tcl
...\......\........\.....\..._fp\$$FlashPro_FPBBALTLPT1.L$$
...\......\........\.....\......\vga.log
...\......\........\.....\......\projectData\vga.pdb
...\......\........\.....\......\vga.pro
...\......\........\.....\....dtf\verify.log
...\......\Thumbs.db
...\参考程序\48M晶振.txt
...\........\VGA.txt
...\........\VGA_CON.vhd
...\........\....zlg\VGA.prj
...\........\.......\viewdraw\vf\project.lst
...\........\.......\........\viewdraw.ini
...\........\.......\synthesis\.recordref
...\........\.......\.........\stdout.log
...\........\.......\.........\traplog.tlg
...\........\.......\.........\vgatest.areasrr
...\........\.......\.........\vgatest.edn
...\........\.......\.........\vgatest.fse
...\........\.......\.........\vgatest.htm
...\........\.......\.........\vgatest.map
...\........\.......\.........\vgatest.sap
...\........\.......\.........\vgatest.sdf
...\........\.......\.........\vgatest.srd
...\........\.......\.........\vgatest.srm
...\........\.......\.........\vgatest.srr
...\........\.......\.........\vgatest.srs
...\........\.......\.........\vgatest.tlg
...\........\.......\.........\vgatest_drc.rpt
...\........\.......\.........\vgatest_sdc.sdc
...\........\.......\.........\vgatest_syn.prd
...\........\.......\.........\syntmp\sap.log
...\........\.......\.........\......\vgatest.msg
...\........\.......\.........\......\vgatest.plg
...\........\.......\.........\......\vgatest_flink.htm
...\........\.......\.........\......\vgatest_srr.htm
...\........\.......\.........\......\vgatest_toc.htm
...\........\.......\.........\vgatest_syn.prj
...\........\.......\.martgen\smartgen.aws
...\........\.......\.imulation\meminit.dat
...\........\.......\..........\modelsim.ini.sav
...\........\.......\..........\modelsim.ini
...\........\.......\hdl\hdlsynchk.tcl
...\........\.......\...\vgatest.v
...\........\.......\designer\impl1\designer.log
...\参数设置.doc
...\vga_OK\pll1.prj
...\......\viewdraw\vf\project.lst
...\......\........\sym\newCore.1
...\......\........\viewdraw.ini
...\......\synthesis\.recordref_modgen
...\......\.........\run_options.txt
...\......\.........\scratchproject.prs
...\......\.........\stdout.log
...\......\.........\traplog.tlg
...\......\.........\vga.areasrr
...\......\.........\vga.edn
...\......\.........\vga.fse
...\......\.........\vga.htm
...\......\.........\vga.map
...\......\.........\vga.pdc
...\......\.........\vga.sap
...\......\.........\vga.sdf
...\......\.........\vga.so
...\......\.........\vga.srd
...\......\.........\vga.srl
...\......\.........\vga.srm
...\......\.........\vga.szr
...\......\.........\vga.tlg
...\......\.........\vga_sdc.sdc
...\......\.........\syntmp\sap.log
...\......\.........\......\sap_log_flink.htm
...\......\.........\......\sap_log_srr.htm
...\......\.........\......\vga.msg
...\......\.........\......\vga.plg
...\......\.........\......\vga_flink.htm
...\......\.........\......\vga_srr.htm
...\......\.........\......\vga_toc.htm
...\......\.........\backup\vga.srr
...\......\.........\vga_syn.prj
...\......\.........\vga.srr
...\......\.........\identify.log
...\......\.........\vga.srs
...\......\.martgen\newCore_work.ixf
...\......\........\.......\newCore.cxf
...\......\........\.......\newCore.gen
...\......\........\.......\newCore.log
...\......\........\.......\newCore.v
...\......\........\smartgen.aws
...\......\.imulation\modelsim.ini.sav
...\......\..........\modelsim.ini
...\......\hdl\vga.v.bak
...\......\...\vga.v
...\......\designer\impl1\designer.log
...\......\........\.....\newCore.ide_des
...\......\........\.....\vga.adb
...\......\........\.....\vga.ide_des
...\......\........\.....\vga.pdb
...\......\........\.....\vga.pdb.depends
...\......\........\.....\vga.tcl
...\......\........\.....\..._fp\$$FlashPro_FPBBALTLPT1.L$$
...\......\........\.....\......\vga.log
...\......\........\.....\......\projectData\vga.pdb
...\......\........\.....\......\vga.pro
...\......\........\.....\....dtf\verify.log
...\......\Thumbs.db
...\参考程序\48M晶振.txt
...\........\VGA.txt
...\........\VGA_CON.vhd
...\........\....zlg\VGA.prj
...\........\.......\viewdraw\vf\project.lst
...\........\.......\........\viewdraw.ini
...\........\.......\synthesis\.recordref
...\........\.......\.........\stdout.log
...\........\.......\.........\traplog.tlg
...\........\.......\.........\vgatest.areasrr
...\........\.......\.........\vgatest.edn
...\........\.......\.........\vgatest.fse
...\........\.......\.........\vgatest.htm
...\........\.......\.........\vgatest.map
...\........\.......\.........\vgatest.sap
...\........\.......\.........\vgatest.sdf
...\........\.......\.........\vgatest.srd
...\........\.......\.........\vgatest.srm
...\........\.......\.........\vgatest.srr
...\........\.......\.........\vgatest.srs
...\........\.......\.........\vgatest.tlg
...\........\.......\.........\vgatest_drc.rpt
...\........\.......\.........\vgatest_sdc.sdc
...\........\.......\.........\vgatest_syn.prd
...\........\.......\.........\syntmp\sap.log
...\........\.......\.........\......\vgatest.msg
...\........\.......\.........\......\vgatest.plg
...\........\.......\.........\......\vgatest_flink.htm
...\........\.......\.........\......\vgatest_srr.htm
...\........\.......\.........\......\vgatest_toc.htm
...\........\.......\.........\vgatest_syn.prj
...\........\.......\.martgen\smartgen.aws
...\........\.......\.imulation\meminit.dat
...\........\.......\..........\modelsim.ini.sav
...\........\.......\..........\modelsim.ini
...\........\.......\hdl\hdlsynchk.tcl
...\........\.......\...\vgatest.v
...\........\.......\designer\impl1\designer.log