文件名称:EDA-test-2
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大学EDA实验的一些代码 都可以完美运行-University of EDA test some of the code works perfect
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下载文件列表
test 2\db\prev_cmp_VHDL_nor.asm.qmsg
......\..\prev_cmp_VHDL_nor.fit.qmsg
......\..\prev_cmp_VHDL_nor.map.qmsg
......\..\prev_cmp_VHDL_nor.qmsg
......\..\prev_cmp_VHDL_nor.sim.qmsg
......\..\prev_cmp_VHDL_nor.tan.qmsg
......\..\VHDL_nor.asm.qmsg
......\..\VHDL_nor.asm_labs.ddb
......\..\VHDL_nor.cbx.xml
......\..\VHDL_nor.cmp.bpm
......\..\VHDL_nor.cmp.cdb
......\..\VHDL_nor.cmp.ecobp
......\..\VHDL_nor.cmp.hdb
......\..\VHDL_nor.cmp.logdb
......\..\VHDL_nor.cmp.rdb
......\..\VHDL_nor.cmp.tdb
......\..\VHDL_nor.cmp0.ddb
......\..\VHDL_nor.db_info
......\..\VHDL_nor.eco.cdb
......\..\VHDL_nor.eds_overflow
......\..\VHDL_nor.fit.qmsg
......\..\VHDL_nor.hier_info
......\..\VHDL_nor.hif
......\..\VHDL_nor.map.bpm
......\..\VHDL_nor.map.cdb
......\..\VHDL_nor.map.ecobp
......\..\VHDL_nor.map.hdb
......\..\VHDL_nor.map.logdb
......\..\VHDL_nor.map.qmsg
......\..\VHDL_nor.map_bb.cdb
......\..\VHDL_nor.map_bb.hdb
......\..\VHDL_nor.map_bb.hdbx
......\..\VHDL_nor.map_bb.logdb
......\..\VHDL_nor.pre_map.cdb
......\..\VHDL_nor.pre_map.hdb
......\..\VHDL_nor.psp
......\..\VHDL_nor.root_partition.cmp.atm
......\..\VHDL_nor.root_partition.cmp.dfp
......\..\VHDL_nor.root_partition.cmp.hdbx
......\..\VHDL_nor.root_partition.cmp.logdb
......\..\VHDL_nor.root_partition.cmp.rcf
......\..\VHDL_nor.root_partition.map.atm
......\..\VHDL_nor.root_partition.map.hdbx
......\..\VHDL_nor.root_partition.map.info
......\..\VHDL_nor.rtlv.hdb
......\..\VHDL_nor.rtlv_sg.cdb
......\..\VHDL_nor.rtlv_sg_swap.cdb
......\..\VHDL_nor.sgdiff.cdb
......\..\VHDL_nor.sgdiff.hdb
......\..\VHDL_nor.signalprobe.cdb
......\..\VHDL_nor.sim.cvwf
......\..\VHDL_nor.sim.hdb
......\..\VHDL_nor.sim.qmsg
......\..\VHDL_nor.sim.rdb
......\..\VHDL_nor.sld_design_entry.sci
......\..\VHDL_nor.sld_design_entry_dsc.sci
......\..\VHDL_nor.syn_hier_info
......\..\VHDL_nor.tan.qmsg
......\..\VHDL_nor.tis_db_list.ddb
......\..\VHDL_nor.tmw_info
......\..\wed.wsf
......\VHDL_nor.asm.rpt
......\VHDL_nor.bsf
......\VHDL_nor.done
......\VHDL_nor.dpf
......\VHDL_nor.fit.rpt
......\VHDL_nor.fit.smsg
......\VHDL_nor.fit.summary
......\VHDL_nor.flow.rpt
......\VHDL_nor.map.rpt
......\VHDL_nor.map.summary
......\VHDL_nor.pin
......\VHDL_nor.pof
......\VHDL_nor.qpf
......\VHDL_nor.qsf
......\VHDL_nor.qws
......\VHDL_nor.sim.rpt
......\VHDL_nor.sof
......\VHDL_nor.tan.rpt
......\VHDL_nor.tan.summary
......\VHDL_nor.vhd
......\VHDL_nor.vhd.bak
......\VHDL_nor.vwf
......\db
test 2
......\..\prev_cmp_VHDL_nor.fit.qmsg
......\..\prev_cmp_VHDL_nor.map.qmsg
......\..\prev_cmp_VHDL_nor.qmsg
......\..\prev_cmp_VHDL_nor.sim.qmsg
......\..\prev_cmp_VHDL_nor.tan.qmsg
......\..\VHDL_nor.asm.qmsg
......\..\VHDL_nor.asm_labs.ddb
......\..\VHDL_nor.cbx.xml
......\..\VHDL_nor.cmp.bpm
......\..\VHDL_nor.cmp.cdb
......\..\VHDL_nor.cmp.ecobp
......\..\VHDL_nor.cmp.hdb
......\..\VHDL_nor.cmp.logdb
......\..\VHDL_nor.cmp.rdb
......\..\VHDL_nor.cmp.tdb
......\..\VHDL_nor.cmp0.ddb
......\..\VHDL_nor.db_info
......\..\VHDL_nor.eco.cdb
......\..\VHDL_nor.eds_overflow
......\..\VHDL_nor.fit.qmsg
......\..\VHDL_nor.hier_info
......\..\VHDL_nor.hif
......\..\VHDL_nor.map.bpm
......\..\VHDL_nor.map.cdb
......\..\VHDL_nor.map.ecobp
......\..\VHDL_nor.map.hdb
......\..\VHDL_nor.map.logdb
......\..\VHDL_nor.map.qmsg
......\..\VHDL_nor.map_bb.cdb
......\..\VHDL_nor.map_bb.hdb
......\..\VHDL_nor.map_bb.hdbx
......\..\VHDL_nor.map_bb.logdb
......\..\VHDL_nor.pre_map.cdb
......\..\VHDL_nor.pre_map.hdb
......\..\VHDL_nor.psp
......\..\VHDL_nor.root_partition.cmp.atm
......\..\VHDL_nor.root_partition.cmp.dfp
......\..\VHDL_nor.root_partition.cmp.hdbx
......\..\VHDL_nor.root_partition.cmp.logdb
......\..\VHDL_nor.root_partition.cmp.rcf
......\..\VHDL_nor.root_partition.map.atm
......\..\VHDL_nor.root_partition.map.hdbx
......\..\VHDL_nor.root_partition.map.info
......\..\VHDL_nor.rtlv.hdb
......\..\VHDL_nor.rtlv_sg.cdb
......\..\VHDL_nor.rtlv_sg_swap.cdb
......\..\VHDL_nor.sgdiff.cdb
......\..\VHDL_nor.sgdiff.hdb
......\..\VHDL_nor.signalprobe.cdb
......\..\VHDL_nor.sim.cvwf
......\..\VHDL_nor.sim.hdb
......\..\VHDL_nor.sim.qmsg
......\..\VHDL_nor.sim.rdb
......\..\VHDL_nor.sld_design_entry.sci
......\..\VHDL_nor.sld_design_entry_dsc.sci
......\..\VHDL_nor.syn_hier_info
......\..\VHDL_nor.tan.qmsg
......\..\VHDL_nor.tis_db_list.ddb
......\..\VHDL_nor.tmw_info
......\..\wed.wsf
......\VHDL_nor.asm.rpt
......\VHDL_nor.bsf
......\VHDL_nor.done
......\VHDL_nor.dpf
......\VHDL_nor.fit.rpt
......\VHDL_nor.fit.smsg
......\VHDL_nor.fit.summary
......\VHDL_nor.flow.rpt
......\VHDL_nor.map.rpt
......\VHDL_nor.map.summary
......\VHDL_nor.pin
......\VHDL_nor.pof
......\VHDL_nor.qpf
......\VHDL_nor.qsf
......\VHDL_nor.qws
......\VHDL_nor.sim.rpt
......\VHDL_nor.sof
......\VHDL_nor.tan.rpt
......\VHDL_nor.tan.summary
......\VHDL_nor.vhd
......\VHDL_nor.vhd.bak
......\VHDL_nor.vwf
......\db
test 2