文件名称:Lattice_FPGA
- 所属分类:
- VHDL编程
- 资源属性:
- [PDF]
- 上传时间:
- 2012-11-26
- 文件大小:
- 2.11mb
- 下载次数:
- 0次
- 提 供 者:
- treacl******
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
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该使用指南适用于初次使用ispLEVER 软件或者不常使用该软件的工程设计人员,它可以帮助你去了解
不同的处理过程,使用各种工具,以及熟悉ispLEVER 产生的各种报告。在进行下一步时,可以准备一
个设计,以此去了解设计的仿真,功耗的计算,静态时序分析,以及以时序驱动的布局和布线,检查由
软件输出的报告等。以此设计为例,你可以练习约束设计的输入,输出信号以及这些信号管脚的分配去
满足系统要求。也可以修改约束条件,达到最佳地利用LatticeEC 的结构和资源,同时实现高性能。该
使用指南覆盖了绝大部分通常的流程和软件选项,那些更大的,时序要求更严的设计则需要更精细的控
制才能满足你对性能和资源利用率要求的目标,在此之前,你必须对这些基本知识有所了解和掌握。-The user guide for first-time ispLEVER software or do not use the software engineering staff, it can help you to understand
Different process, using a variety of tools, and familiar with the ispLEVER for a variety of reports. Before going further, you can prepare a
A design, in order to understand the design of the simulation, power calculation, static timing analysis, as well as timing-driven place and route, check the
Software output reports. This design, for example, you can practice the design constraints of input and output signals and the distribution of these signals to pins
Meet the system requirements. Constraints can also be modified to achieve the best use of LatticeEC structure and resources, while achieving high performance. The
Guide covers the most common processes and software options, those larger, more stringent timing requirements of the design of more sophisticated control is required
System to meet your requirements for performance and resource utilization go
不同的处理过程,使用各种工具,以及熟悉ispLEVER 产生的各种报告。在进行下一步时,可以准备一
个设计,以此去了解设计的仿真,功耗的计算,静态时序分析,以及以时序驱动的布局和布线,检查由
软件输出的报告等。以此设计为例,你可以练习约束设计的输入,输出信号以及这些信号管脚的分配去
满足系统要求。也可以修改约束条件,达到最佳地利用LatticeEC 的结构和资源,同时实现高性能。该
使用指南覆盖了绝大部分通常的流程和软件选项,那些更大的,时序要求更严的设计则需要更精细的控
制才能满足你对性能和资源利用率要求的目标,在此之前,你必须对这些基本知识有所了解和掌握。-The user guide for first-time ispLEVER software or do not use the software engineering staff, it can help you to understand
Different process, using a variety of tools, and familiar with the ispLEVER for a variety of reports. Before going further, you can prepare a
A design, in order to understand the design of the simulation, power calculation, static timing analysis, as well as timing-driven place and route, check the
Software output reports. This design, for example, you can practice the design constraints of input and output signals and the distribution of these signals to pins
Meet the system requirements. Constraints can also be modified to achieve the best use of LatticeEC structure and resources, while achieving high performance. The
Guide covers the most common processes and software options, those larger, more stringent timing requirements of the design of more sophisticated control is required
System to meet your requirements for performance and resource utilization go
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Lattice_FPGA开发入门.pdf