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文件名称:an497_design_example

  • 所属分类：
  • VHDL编程
  • 资源属性：
  • [VHDL] [源码]
  • 上传时间：
  • 2012-11-26
  • 文件大小：
  • 1.51mb
  • 下载次数：
  • 0次
  • 提 供 者：
  • Sil***
  • 相关连接：
  • 无
  • 下载说明：
  • 别用迅雷下载，失败请重下，重下不扣分！
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LCD driver VHDL example
(系统自动生成,下载前可以参看下载内容)

下载文件列表

LCD_Controller_Altera_MAX_II_CPLD_Design_Exampler\code

.................................................\....\lcd_controller.v

.................................................\modelsim

.................................................\........\lcd_controller.cr.mti

.................................................\........\lcd_controller.mpf

.................................................\........\lcd_controller.v

.................................................\........\lcd_testbench.v

.................................................\........\transcript

.................................................\........\vsim.wlf

.................................................\........\wave.bmp

.................................................\........\wave.do

.................................................\........\work

.................................................\........\....\@u@f@m2

.................................................\........\....\.......\verilog.psm

.................................................\........\....\.......\_primary.dat

.................................................\........\....\.......\_primary.vhd

.................................................\........\....\@u@f@m2_altufm_parallel_bmm

.................................................\........\....\...........................\verilog.psm

.................................................\........\....\...........................\_primary.dat

.................................................\........\....\...........................\_primary.vhd

.................................................\........\....\divider

.................................................\........\....\.......\verilog.psm

.................................................\........\....\.......\_primary.dat

.................................................\........\....\.......\_primary.vhd

.................................................\........\....\fsm

.................................................\........\....\...\verilog.psm

.................................................\........\....\...\_primary.dat

.................................................\........\....\...\_primary.vhd

.................................................\........\....\lcd_controller

.................................................\........\....\..............\verilog.psm

.................................................\........\....\..............\_primary.dat

.................................................\........\....\..............\_primary.vhd

.................................................\........\....\lcd_testbench

.................................................\........\....\.............\verilog.psm

.................................................\........\....\.............\_primary.dat

.................................................\........\....\.............\_primary.vhd

.................................................\........\....\_info

.................................................\quartus

.................................................\.......\db

.................................................\.......\..\lcd_controller.asm.qmsg

.................................................\.......\..\lcd_controller.asm_labs.ddb

.................................................\.......\..\lcd_controller.cbx.xml

.................................................\.......\..\lcd_controller.cmp.cdb

.................................................\.......\..\lcd_controller.cmp.hdb

.................................................\.......\..\lcd_controller.cmp.logdb

.................................................\.......\..\lcd_controller.cmp.rdb

.................................................\.......\..\lcd_controller.cmp.tdb

.................................................\.......\..\lcd_controller.cmp0.ddb

.................................................\.......\..\lcd_controller.dbp

.................................................\.......\..\lcd_controller.db_info

.................................................\.......\..\lcd_controll

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