文件名称:FlashLock_test
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pdf actel fpga verilog FLASH读写-pdf actel fpga verilog FLASH write
(系统自动生成,下载前可以参看下载内容)
下载文件列表
FlashLock_test\designer\impl1\designer.log
..............\........\.....\my_inv.adb
..............\........\.....\my_inv.dat
..............\........\.....\my_inv.ide_des
..............\........\.....\my_inv.pdb
..............\........\.....\my_inv.pdb.depends
..............\........\.....\my_inv.stp
..............\........\.....\my_inv.tcl
..............\FlashLock_test.prj
..............\hdl\my_inv.v
..............\simulation\modelsim.ini
..............\.martgen\smartgen.aws
..............\.ynthesis\my_inv.areasrr
..............\.........\my_inv.edn
..............\.........\my_inv.fse
..............\.........\my_inv.htm
..............\.........\my_inv.map
..............\.........\my_inv.pdc
..............\.........\my_inv.sap
..............\.........\my_inv.sdf
..............\.........\my_inv.so
..............\.........\my_inv.srd
..............\.........\my_inv.srm
..............\.........\my_inv.srr
..............\.........\my_inv.srs
..............\.........\my_inv.szr
..............\.........\my_inv.tlg
..............\.........\my_inv_sdc.sdc
..............\.........\my_inv_syn.prj
..............\.........\run_options.txt
..............\.........\stdout.log
..............\.........\.yntmp\my_inv.plg
..............\.........\......\my_inv_flink.htm
..............\.........\......\my_inv_srr.htm
..............\.........\......\my_inv_toc.htm
..............\.........\......\sap.log
..............\viewdraw\vf\project.lst
..............\........\viewdraw.ini
..............\designer\impl1\my_inv.dtf
..............\........\.....\simulation
..............\........\impl1
..............\synthesis\backup
..............\.........\coreip
..............\.........\syntmp
..............\viewdraw\sch
..............\........\sym
..............\........\vf
..............\........\wir
..............\component
..............\constraint
..............\coreconsole
..............\designer
..............\hdl
..............\phy_synthesis
..............\simulation
..............\smartgen
..............\stimulus
..............\synthesis
..............\viewdraw
FlashLock_test
..............\........\.....\my_inv.adb
..............\........\.....\my_inv.dat
..............\........\.....\my_inv.ide_des
..............\........\.....\my_inv.pdb
..............\........\.....\my_inv.pdb.depends
..............\........\.....\my_inv.stp
..............\........\.....\my_inv.tcl
..............\FlashLock_test.prj
..............\hdl\my_inv.v
..............\simulation\modelsim.ini
..............\.martgen\smartgen.aws
..............\.ynthesis\my_inv.areasrr
..............\.........\my_inv.edn
..............\.........\my_inv.fse
..............\.........\my_inv.htm
..............\.........\my_inv.map
..............\.........\my_inv.pdc
..............\.........\my_inv.sap
..............\.........\my_inv.sdf
..............\.........\my_inv.so
..............\.........\my_inv.srd
..............\.........\my_inv.srm
..............\.........\my_inv.srr
..............\.........\my_inv.srs
..............\.........\my_inv.szr
..............\.........\my_inv.tlg
..............\.........\my_inv_sdc.sdc
..............\.........\my_inv_syn.prj
..............\.........\run_options.txt
..............\.........\stdout.log
..............\.........\.yntmp\my_inv.plg
..............\.........\......\my_inv_flink.htm
..............\.........\......\my_inv_srr.htm
..............\.........\......\my_inv_toc.htm
..............\.........\......\sap.log
..............\viewdraw\vf\project.lst
..............\........\viewdraw.ini
..............\designer\impl1\my_inv.dtf
..............\........\.....\simulation
..............\........\impl1
..............\synthesis\backup
..............\.........\coreip
..............\.........\syntmp
..............\viewdraw\sch
..............\........\sym
..............\........\vf
..............\........\wir
..............\component
..............\constraint
..............\coreconsole
..............\designer
..............\hdl
..............\phy_synthesis
..............\simulation
..............\smartgen
..............\stimulus
..............\synthesis
..............\viewdraw
FlashLock_test