文件名称:DFF
介绍说明－－下载内容均来自于网络，请自行研究使用
actel fpga D触发器 verilog描述-pdf actel fpga d
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DFF\designer\impl1\designer.log
...\........\.....\DFF.ide_des
...\........\.....\DFF_1.ide_des
...\........\.....\my_dff.adb
...\........\.....\my_dff.dat
...\........\.....\........tf\verify.log
...\........\.....\my_dff.ide_des
...\........\.....\my_dff.pdb
...\........\.....\my_dff.pdb.depends
...\........\.....\my_dff.stp
...\........\.....\my_dff.tcl
...\DFF.prj
...\hdl\my_dff.v
...\simulation\modelsim.ini
...\..........\modelsim.ini.sav
...\.martgen\smartgen.aws
...\.ynthesis\.recordref
...\.........\DFF.areasrr
...\.........\DFF.edn
...\.........\DFF.fse
...\.........\DFF.htm
...\.........\DFF.map
...\.........\DFF.pdc
...\.........\DFF.sap
...\.........\DFF.sdf
...\.........\DFF.so
...\.........\DFF.srd
...\.........\DFF.srm
...\.........\DFF.srr
...\.........\DFF.srs
...\.........\DFF.szr
...\.........\DFF.tlg
...\.........\DFF_sdc.sdc
...\.........\DFF_syn.prj
...\.........\my_dff.areasrr
...\.........\my_dff.edn
...\.........\my_dff.fse
...\.........\my_dff.htm
...\.........\my_dff.map
...\.........\my_dff.pdc
...\.........\my_dff.sap
...\.........\my_dff.sdf
...\.........\my_dff.so
...\.........\my_dff.srd
...\.........\my_dff.srm
...\.........\my_dff.srr
...\.........\my_dff.srs
...\.........\my_dff.szr
...\.........\my_dff.tlg
...\.........\my_dff_sdc.sdc
...\.........\my_dff_syn.prj
...\.........\run_options.txt
...\.........\stdout.log
...\.........\.yntmp\DFF.plg
...\.........\......\DFF_flink.htm
...\.........\......\DFF_srr.htm
...\.........\......\DFF_toc.htm
...\.........\......\my_dff.plg
...\.........\......\my_dff_flink.htm
...\.........\......\my_dff_srr.htm
...\.........\......\my_dff_toc.htm
...\.........\......\sap.log
...\.........\traplog.tlg
...\viewdraw\vf\project.lst
...\........\viewdraw.ini
...\designer\impl1\my_dff.dtf
...\........\.....\simulation
...\........\impl1
...\synthesis\backup
...\.........\coreip
...\.........\syntmp
...\viewdraw\sch
...\........\sym
...\........\vf
...\........\wir
...\component
...\constraint
...\coreconsole
...\designer
...\hdl
...\phy_synthesis
...\simulation
...\smartgen
...\stimulus
...\synthesis
...\viewdraw
DFF
...\........\.....\DFF.ide_des
...\........\.....\DFF_1.ide_des
...\........\.....\my_dff.adb
...\........\.....\my_dff.dat
...\........\.....\........tf\verify.log
...\........\.....\my_dff.ide_des
...\........\.....\my_dff.pdb
...\........\.....\my_dff.pdb.depends
...\........\.....\my_dff.stp
...\........\.....\my_dff.tcl
...\DFF.prj
...\hdl\my_dff.v
...\simulation\modelsim.ini
...\..........\modelsim.ini.sav
...\.martgen\smartgen.aws
...\.ynthesis\.recordref
...\.........\DFF.areasrr
...\.........\DFF.edn
...\.........\DFF.fse
...\.........\DFF.htm
...\.........\DFF.map
...\.........\DFF.pdc
...\.........\DFF.sap
...\.........\DFF.sdf
...\.........\DFF.so
...\.........\DFF.srd
...\.........\DFF.srm
...\.........\DFF.srr
...\.........\DFF.srs
...\.........\DFF.szr
...\.........\DFF.tlg
...\.........\DFF_sdc.sdc
...\.........\DFF_syn.prj
...\.........\my_dff.areasrr
...\.........\my_dff.edn
...\.........\my_dff.fse
...\.........\my_dff.htm
...\.........\my_dff.map
...\.........\my_dff.pdc
...\.........\my_dff.sap
...\.........\my_dff.sdf
...\.........\my_dff.so
...\.........\my_dff.srd
...\.........\my_dff.srm
...\.........\my_dff.srr
...\.........\my_dff.srs
...\.........\my_dff.szr
...\.........\my_dff.tlg
...\.........\my_dff_sdc.sdc
...\.........\my_dff_syn.prj
...\.........\run_options.txt
...\.........\stdout.log
...\.........\.yntmp\DFF.plg
...\.........\......\DFF_flink.htm
...\.........\......\DFF_srr.htm
...\.........\......\DFF_toc.htm
...\.........\......\my_dff.plg
...\.........\......\my_dff_flink.htm
...\.........\......\my_dff_srr.htm
...\.........\......\my_dff_toc.htm
...\.........\......\sap.log
...\.........\traplog.tlg
...\viewdraw\vf\project.lst
...\........\viewdraw.ini
...\designer\impl1\my_dff.dtf
...\........\.....\simulation
...\........\impl1
...\synthesis\backup
...\.........\coreip
...\.........\syntmp
...\viewdraw\sch
...\........\sym
...\........\vf
...\........\wir
...\component
...\constraint
...\coreconsole
...\designer
...\hdl
...\phy_synthesis
...\simulation
...\smartgen
...\stimulus
...\synthesis
...\viewdraw
DFF