文件名称:assignment_1.6
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one of the sample of VHDL code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
assignment 1.6\db
..............\..\add_sub_7nh.tdf
..............\..\P4_4.asm.qmsg
..............\..\P4_4.cbx.xml
..............\..\P4_4.cmp.cdb
..............\..\P4_4.cmp.hdb
..............\..\P4_4.cmp.logdb
..............\..\P4_4.cmp.rdb
..............\..\P4_4.cmp.tdb
..............\..\P4_4.cmp0.ddb
..............\..\P4_4.db_info
..............\..\P4_4.eco.cdb
..............\..\P4_4.eds_overflow
..............\..\P4_4.fit.qmsg
..............\..\P4_4.fnsim.cdb
..............\..\P4_4.fnsim.hdb
..............\..\P4_4.fnsim.qmsg
..............\..\P4_4.hier_info
..............\..\P4_4.hif
..............\..\P4_4.lpc.html
..............\..\P4_4.lpc.rdb
..............\..\P4_4.lpc.txt
..............\..\P4_4.map.cdb
..............\..\P4_4.map.hdb
..............\..\P4_4.map.logdb
..............\..\P4_4.map.qmsg
..............\..\P4_4.pre_map.cdb
..............\..\P4_4.pre_map.hdb
..............\..\P4_4.rtlv.hdb
..............\..\P4_4.rtlv_sg.cdb
..............\..\P4_4.rtlv_sg_swap.cdb
..............\..\P4_4.sgdiff.cdb
..............\..\P4_4.sgdiff.hdb
..............\..\P4_4.sim.cvwf
..............\..\P4_4.sim.hdb
..............\..\P4_4.sim.qmsg
..............\..\P4_4.sim.rdb
..............\..\P4_4.simfam
..............\..\P4_4.sld_design_entry.sci
..............\..\P4_4.sld_design_entry_dsc.sci
..............\..\P4_4.syn_hier_info
..............\..\P4_4.tan.qmsg
..............\..\P4_4.tis_db_list.ddb
..............\..\P4_4.tmw_info
..............\..\prev_cmp_P4_4.asm.qmsg
..............\..\prev_cmp_P4_4.fit.qmsg
..............\..\prev_cmp_P4_4.map.qmsg
..............\..\prev_cmp_P4_4.qmsg
..............\..\prev_cmp_P4_4.sim.qmsg
..............\..\prev_cmp_P4_4.tan.qmsg
..............\..\wed.wsf
..............\DU.bsf
..............\DU.vhd
..............\DU.vhd.bak
..............\incremental_db
..............\..............\compiled_partitions
..............\..............\...................\P4_4.root_partition.map.kpt
..............\..............\README
..............\P4_4.asm.rpt
..............\P4_4.bdf
..............\P4_4.done
..............\P4_4.fit.rpt
..............\P4_4.fit.summary
..............\P4_4.flow.rpt
..............\P4_4.map.rpt
..............\P4_4.map.summary
..............\P4_4.pin
..............\P4_4.pof
..............\P4_4.qpf
..............\P4_4.qsf
..............\P4_4.qws
..............\P4_4.sim.rpt
..............\P4_4.sof
..............\P4_4.tan.rpt
..............\P4_4.tan.summary
..............\P4_4.vwf
..............\P4_4_1.pof
..............\P4_4_description.txt
..............\regn.bsf
..............\regn.vhd
..............\shiftLreg8.bsf
..............\shiftLreg8.vhd
..............\shiftLreg8.vhd.bak
..............\shiftRreg4.bsf
..............\shiftRreg4.vhd
..............\shiftRreg4.vhd.bak
..............\..\add_sub_7nh.tdf
..............\..\P4_4.asm.qmsg
..............\..\P4_4.cbx.xml
..............\..\P4_4.cmp.cdb
..............\..\P4_4.cmp.hdb
..............\..\P4_4.cmp.logdb
..............\..\P4_4.cmp.rdb
..............\..\P4_4.cmp.tdb
..............\..\P4_4.cmp0.ddb
..............\..\P4_4.db_info
..............\..\P4_4.eco.cdb
..............\..\P4_4.eds_overflow
..............\..\P4_4.fit.qmsg
..............\..\P4_4.fnsim.cdb
..............\..\P4_4.fnsim.hdb
..............\..\P4_4.fnsim.qmsg
..............\..\P4_4.hier_info
..............\..\P4_4.hif
..............\..\P4_4.lpc.html
..............\..\P4_4.lpc.rdb
..............\..\P4_4.lpc.txt
..............\..\P4_4.map.cdb
..............\..\P4_4.map.hdb
..............\..\P4_4.map.logdb
..............\..\P4_4.map.qmsg
..............\..\P4_4.pre_map.cdb
..............\..\P4_4.pre_map.hdb
..............\..\P4_4.rtlv.hdb
..............\..\P4_4.rtlv_sg.cdb
..............\..\P4_4.rtlv_sg_swap.cdb
..............\..\P4_4.sgdiff.cdb
..............\..\P4_4.sgdiff.hdb
..............\..\P4_4.sim.cvwf
..............\..\P4_4.sim.hdb
..............\..\P4_4.sim.qmsg
..............\..\P4_4.sim.rdb
..............\..\P4_4.simfam
..............\..\P4_4.sld_design_entry.sci
..............\..\P4_4.sld_design_entry_dsc.sci
..............\..\P4_4.syn_hier_info
..............\..\P4_4.tan.qmsg
..............\..\P4_4.tis_db_list.ddb
..............\..\P4_4.tmw_info
..............\..\prev_cmp_P4_4.asm.qmsg
..............\..\prev_cmp_P4_4.fit.qmsg
..............\..\prev_cmp_P4_4.map.qmsg
..............\..\prev_cmp_P4_4.qmsg
..............\..\prev_cmp_P4_4.sim.qmsg
..............\..\prev_cmp_P4_4.tan.qmsg
..............\..\wed.wsf
..............\DU.bsf
..............\DU.vhd
..............\DU.vhd.bak
..............\incremental_db
..............\..............\compiled_partitions
..............\..............\...................\P4_4.root_partition.map.kpt
..............\..............\README
..............\P4_4.asm.rpt
..............\P4_4.bdf
..............\P4_4.done
..............\P4_4.fit.rpt
..............\P4_4.fit.summary
..............\P4_4.flow.rpt
..............\P4_4.map.rpt
..............\P4_4.map.summary
..............\P4_4.pin
..............\P4_4.pof
..............\P4_4.qpf
..............\P4_4.qsf
..............\P4_4.qws
..............\P4_4.sim.rpt
..............\P4_4.sof
..............\P4_4.tan.rpt
..............\P4_4.tan.summary
..............\P4_4.vwf
..............\P4_4_1.pof
..............\P4_4_description.txt
..............\regn.bsf
..............\regn.vhd
..............\shiftLreg8.bsf
..............\shiftLreg8.vhd
..............\shiftLreg8.vhd.bak
..............\shiftRreg4.bsf
..............\shiftRreg4.vhd
..............\shiftRreg4.vhd.bak