文件名称:fifo_syn
介绍说明－－下载内容均来自于网络，请自行研究使用
本源码是用VERILOG实现FIFO的读取，并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
(系统自动生成,下载前可以参看下载内容)
下载文件列表
fifo_syn\fifo_syn_flag.v
........\fifo_syn_ram.v
........\fifo_syn_rdaddr_gen.v
........\fifo_syn_top.v
........\fifo_syn_wraddr_gen.v
........\fifo_top_tb.v
........\使用说明请参看右侧注释====〉〉.txt
........\同步FIFO设计.doc
fifo_syn
........\fifo_syn_ram.v
........\fifo_syn_rdaddr_gen.v
........\fifo_syn_top.v
........\fifo_syn_wraddr_gen.v
........\fifo_top_tb.v
........\使用说明请参看右侧注释====〉〉.txt
........\同步FIFO设计.doc
fifo_syn