文件名称:Design-of-general-purpose-registers-vhdl-language.
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寄存器设计，以VHDL语言设计模拟一个通用寄存器。可供初学者学习。-Register is designed to simulate a VHDL language design general-purpose registers. For beginners to learn.
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Design-of-general-purpose-registers-vhdl-language.doc