文件名称:uart
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uart设计 包括调试程序 uart设计 包括调试程序-uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL uart verilog HDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart\Mcu\UartTest\FpgaInc.h
....\...\........\main.c
....\...\........\stdinc.h
....\...\........\UartCtrl.c
....\...\........\UartCtrl.h
....\...\........\UartTest.dep
....\...\........\UartTest.ewd
....\...\........\UartTest.ewp
....\...\........\UartTest.eww
....\...\........\settings\test.cspy.bat
....\...\........\........\test.dbgdt
....\...\........\........\test.dni
....\...\........\........\test.wsdt
....\...\........\........\UartTest.cspy.bat
....\...\........\........\UartTest.dni
....\...\........\........\UartTest.wsdt
....\UART设计文档.pdf
....\读我.txt
....\fpga\V0p10\top.bsf
....\....\.....\uart.asm.rpt
....\....\.....\uart.cdf
....\....\.....\uart.done
....\....\.....\uart.dpf
....\....\.....\uart.fit.rpt
....\....\.....\uart.fit.smsg
....\....\.....\uart.fit.summary
....\....\.....\uart.map.smsg
....\....\.....\uart.map.summary
....\....\.....\uart.pin
....\....\.....\uart.pof
....\....\.....\uart.qpf
....\....\.....\uart.qsf
....\....\.....\uart.sof
....\....\.....\uart.tan.rpt
....\....\.....\uart.tan.summary
....\....\.....\uart_description.txt
....\....\.....\db\uart.db_info
....\....\.....\..\uart.map.qmsg
....\....\.....\..\uart.cbx.xml
....\....\.....\..\uart.hif
....\....\.....\..\uart.hier_info
....\....\.....\..\uart.rtlv_sg.cdb
....\....\.....\..\uart.rtlv.hdb
....\....\.....\..\uart.rtlv_sg_swap.cdb
....\....\.....\..\uart.lpc.txt
....\....\.....\..\uart.lpc.html
....\....\.....\..\uart.lpc.rdb
....\....\.....\..\uart.pre_map.hdb
....\....\.....\..\uart.pre_map.cdb
....\....\.....\..\uart.smp_dump.txt
....\....\.....\..\uart.map_bb.logdb
....\....\.....\..\uart.sgdiff.cdb
....\....\.....\..\uart.sgdiff.hdb
....\....\.....\..\uart.sld_design_entry_dsc.sci
....\....\.....\..\uart.syn_hier_info
....\....\.....\..\uart.map_bb.cdb
....\....\.....\..\uart.map_bb.hdb
....\....\.....\..\uart.map.ecobp
....\....\.....\..\uart.map.kpt
....\....\.....\..\uart.cmp_merge.kpt
....\....\.....\..\uart.map.cdb
....\....\.....\..\uart.map.hdb
....\....\.....\..\uart.map.logdb
....\....\.....\..\uart.map.bpm
....\....\.....\..\uart.cmp.rdb
....\....\.....\..\uart.tis_db_list.ddb
....\....\.....\..\uart.sld_design_entry.sci
....\....\.....\..\uart.eco.cdb
....\....\.....\src\ebi.v
....\....\.....\...\rxd.v
....\....\.....\...\top.v
....\....\.....\...\txd.v
....\....\.....\...\uart.v
....\....\.....\...\divider.v.bak
....\....\.....\...\divider.v
....\....\.....\testbench\ModelSim.jpg
....\....\.....\.........\tcl_stacktrace.txt
....\....\.....\.........\top_tb.v
....\....\.....\.........\transcript
....\....\.....\.........\uart.cr.mti
....\....\.....\.........\uart.mpf
....\....\.....\.........\vish_stacktrace.vstf
....\....\.....\.........\vsim.wlf
....\....\.....\.........\vsim_stacktrace.vstf
....\....\.....\.........\cycloneII_v\_info
....\....\.....\.........\work\_info
....\....\.....\.........\....\divider\verilog.asm
....\....\.....\.........\....\.......\_primary.dat
....\....\.....\.........\....\.......\_primary.vhd
....\....\.....\.........\....\....sion\verilog.asm
....\....\.....\.........\....\........\_primary.dat
....\....\.....\.........\....\........\_primary.vhd
....\....\.....\.........\....\ebi\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\rxd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\top\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\...\........\main.c
....\...\........\stdinc.h
....\...\........\UartCtrl.c
....\...\........\UartCtrl.h
....\...\........\UartTest.dep
....\...\........\UartTest.ewd
....\...\........\UartTest.ewp
....\...\........\UartTest.eww
....\...\........\settings\test.cspy.bat
....\...\........\........\test.dbgdt
....\...\........\........\test.dni
....\...\........\........\test.wsdt
....\...\........\........\UartTest.cspy.bat
....\...\........\........\UartTest.dni
....\...\........\........\UartTest.wsdt
....\UART设计文档.pdf
....\读我.txt
....\fpga\V0p10\top.bsf
....\....\.....\uart.asm.rpt
....\....\.....\uart.cdf
....\....\.....\uart.done
....\....\.....\uart.dpf
....\....\.....\uart.fit.rpt
....\....\.....\uart.fit.smsg
....\....\.....\uart.fit.summary
....\....\.....\uart.map.smsg
....\....\.....\uart.map.summary
....\....\.....\uart.pin
....\....\.....\uart.pof
....\....\.....\uart.qpf
....\....\.....\uart.qsf
....\....\.....\uart.sof
....\....\.....\uart.tan.rpt
....\....\.....\uart.tan.summary
....\....\.....\uart_description.txt
....\....\.....\db\uart.db_info
....\....\.....\..\uart.map.qmsg
....\....\.....\..\uart.cbx.xml
....\....\.....\..\uart.hif
....\....\.....\..\uart.hier_info
....\....\.....\..\uart.rtlv_sg.cdb
....\....\.....\..\uart.rtlv.hdb
....\....\.....\..\uart.rtlv_sg_swap.cdb
....\....\.....\..\uart.lpc.txt
....\....\.....\..\uart.lpc.html
....\....\.....\..\uart.lpc.rdb
....\....\.....\..\uart.pre_map.hdb
....\....\.....\..\uart.pre_map.cdb
....\....\.....\..\uart.smp_dump.txt
....\....\.....\..\uart.map_bb.logdb
....\....\.....\..\uart.sgdiff.cdb
....\....\.....\..\uart.sgdiff.hdb
....\....\.....\..\uart.sld_design_entry_dsc.sci
....\....\.....\..\uart.syn_hier_info
....\....\.....\..\uart.map_bb.cdb
....\....\.....\..\uart.map_bb.hdb
....\....\.....\..\uart.map.ecobp
....\....\.....\..\uart.map.kpt
....\....\.....\..\uart.cmp_merge.kpt
....\....\.....\..\uart.map.cdb
....\....\.....\..\uart.map.hdb
....\....\.....\..\uart.map.logdb
....\....\.....\..\uart.map.bpm
....\....\.....\..\uart.cmp.rdb
....\....\.....\..\uart.tis_db_list.ddb
....\....\.....\..\uart.sld_design_entry.sci
....\....\.....\..\uart.eco.cdb
....\....\.....\src\ebi.v
....\....\.....\...\rxd.v
....\....\.....\...\top.v
....\....\.....\...\txd.v
....\....\.....\...\uart.v
....\....\.....\...\divider.v.bak
....\....\.....\...\divider.v
....\....\.....\testbench\ModelSim.jpg
....\....\.....\.........\tcl_stacktrace.txt
....\....\.....\.........\top_tb.v
....\....\.....\.........\transcript
....\....\.....\.........\uart.cr.mti
....\....\.....\.........\uart.mpf
....\....\.....\.........\vish_stacktrace.vstf
....\....\.....\.........\vsim.wlf
....\....\.....\.........\vsim_stacktrace.vstf
....\....\.....\.........\cycloneII_v\_info
....\....\.....\.........\work\_info
....\....\.....\.........\....\divider\verilog.asm
....\....\.....\.........\....\.......\_primary.dat
....\....\.....\.........\....\.......\_primary.vhd
....\....\.....\.........\....\....sion\verilog.asm
....\....\.....\.........\....\........\_primary.dat
....\....\.....\.........\....\........\_primary.vhd
....\....\.....\.........\....\ebi\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\rxd\verilog.asm
....\....\.....\.........\....\...\_primary.dat
....\....\.....\.........\....\...\_primary.vhd
....\....\.....\.........\....\top\verilog.asm
....\....\.....\.........\....\...\_primary.dat