This example application demonstrates the interrupt preemption and

tail-chaining capabilities of Cortex-M3 microprocessor and NVIC. Nested

interrupts are synthesized when the interrupts have the same priority,

increasing priorities, and decreasing priorities. With increasing

priorities, preemption will occur in the other two cases tail-chaining

will occur. The currently pending interrupts and the currently executing

interrupt will be displayed on the OLED GPIO pins B0, B1 and B2 will be

asserted upon interrupt handler entry and de-asserted before interrupt

handler exit so that the off-to-on time can be observed with a scope or

logic analyzer to see the speed of tail-chaining (for the two cases where

tail-chaining is occurring).-This example application demonstrates the interrupt preemption and

tail-chaining capabilities of Cortex-M3 microprocessor and NVIC.　Nested

interrupts are synthesized when the interrupts have the same priority,

increasing priorities, and decreasing priorities.　With increasing

priorities, preemption will occur　in the other two cases tail-chaining

will occur.　The currently pending interrupts and the currently executing

interrupt will be displayed on the OLED　GPIO pins B0, B1 and B2 will be

asserted upon interrupt handler entry and de-asserted before interrupt

handler exit so that the off-to-on time can be observed with a scope or

logic analyzer to see the speed of tail-chaining (for the two cases where

tail-chaining is occurring).