文件名称:crc

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 3.97mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 王**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

CRC用来对所输入的序列进行检测 看是不是有错误-CRC is use to detect whether the line right or wrong
(系统自动生成,下载前可以参看下载内容)

下载文件列表

crc\crc.qpf

...\crc.qsf

...\db\crc.db_info

...\..\crc.rtlv_sg.cdb

...\..\crc.cmp0.ddb

...\..\crc.cmp.rdb

...\..\crc.eda.qmsg

...\..\crc.rtlv_sg_swap.cdb

...\..\prev_cmp_crc.map.qmsg

...\..\prev_cmp_crc.fit.qmsg

...\..\crc.eco.cdb

...\..\crc.cbx.xml

...\..\crc.hif

...\..\crc.hier_info

...\..\crc.fit.qmsg

...\..\prev_cmp_crc.asm.qmsg

...\..\prev_cmp_crc.tan.qmsg

...\..\prev_cmp_crc.eda.qmsg

...\..\prev_cmp_crc.qmsg

...\..\crc.sld_design_entry.sci

...\..\crc.psp

...\..\crc.tmw_info

...\..\crc.map.qmsg

...\..\crc.rtlv.hdb

...\..\crc.pre_map.hdb

...\..\crc.pre_map.cdb

...\..\crc.root_partition.map.info

...\..\crc.syn_hier_info

...\..\crc.map_bb.logdb

...\..\crc.sgdiff.cdb

...\..\crc.root_partition.map.atm

...\..\crc.root_partition.map.hdbx

...\..\crc.sgdiff.hdb

...\..\crc.map_bb.hdbx

...\..\crc.cmp.logdb

...\..\crc.map.ecobp

...\..\crc.sld_design_entry_dsc.sci

...\..\crc.asm.qmsg

...\..\crc.map_bb.cdb

...\..\crc.map_bb.hdb

...\..\crc.map.logdb

...\..\crc.map.cdb

...\..\crc.map.hdb

...\..\crc.asm_labs.ddb

...\..\crc.map.bpm

...\..\crc.tan.qmsg

...\..\crc.cmp.cdb

...\..\crc.cmp.ecobp

...\..\crc.cmp.hdb

...\..\crc.cmp.bpm

...\..\crc.root_partition.cmp.logdb

...\..\crc.root_partition.cmp.dfp

...\..\crc.cmp.tdb

...\..\crc.tis_db_list.ddb

...\..\crc.signalprobe.cdb

...\..\crc.root_partition.cmp.rcf

...\..\crc.root_partition.cmp.hdbx

...\..\crc.root_partition.cmp.atm

...\crc.map.summary

...\crc.pin

...\crc.fit.smsg

...\crc.fit.summary

...\crc.sof

...\crc.pof

...\crc.tan.summary

...\simulation\modelsim\crc_modelsim.xrf

...\..........\........\crc.vo

...\..........\........\crc_v.sdo

...\..........\........\crc.sft

...\..........\........\crc_run_msim_rtl_verilog.do

...\..........\........\verilog_libs\lpm_ver\_info

...\..........\........\............\.......\@l@p@m_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\_primary.vhd

...\..........\........\............\.......\................................................\verilog.asm

...\..........\........\............\.......\................................................\_primary.dat

...\..........\........\............\.......\........h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.vhd

...\..........\........\............\.......\....................................\verilog.asm

...\..........\........\............\.......\....................................\_primary.dat

...\..........\........\............\.......\........d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.vhd

...\..........\........\............\.......\....................................\verilog.asm

...\..........\........\............\.......\....................................\_primary.dat

...\..........\........\............\.......\lpm_constant\_primary.vhd

...\..........\........\............\.......\............\verilog.asm

...\..........\........\............\.......\............\_primary.dat

...\..........\........\............\.......\....inv\_primary.vhd

...\..........\........\............\.......\.......\verilog.asm

...\..........\........\............\.......\.......\_primary.dat

...\..........\........\............\.......\....and\_primary.vhd

...\..........\........\............\.......\.......\verilog.asm

...\..........\........\............\.......\.......\_primary.dat

...\..........\........\............\.......\....or\_primary.vhd

...\..........\........\............\.......\......\verilog.asm

...\..........\........\............\.......\......\_primary.dat

...\..........\........\............\.......\....xor\_primary.vhd

...\..........\........\............\.......\.......\verilog.asm

...\..........\........\............\.......\.......\_primary.dat

...\..........\........\............\.......\....bustri\_primary.vhd

...\..........\........\............\.......\..........\verilog.asm

...\..........\........\............\.......\..........\_primary.dat

...\..........\........\............\.......\....mux\_primary.vhd

...\..........\........\............\.......\.......\verilog.asm

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