文件名称:DigitalWatch
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Digital watch write in Verilog HDL language simulate the real clock in Atera DE2 development board
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下载文件列表
DigitalWatch\clkDivVar.v
............\dec7seg.v
............\DigitalWatch_v1_0.qpf
............\DigitalWatch_v1_0.qsf
............\DigitalWatch_v1_0.v
............\up_down_counter.v
............\up_down_limit_out_counter.v
DigitalWatch
............\dec7seg.v
............\DigitalWatch_v1_0.qpf
............\DigitalWatch_v1_0.qsf
............\DigitalWatch_v1_0.v
............\up_down_counter.v
............\up_down_limit_out_counter.v
DigitalWatch