文件名称:CY7c68013_fpga_write_sram
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA和USB经行通讯的源代码，很好很强大，希望对大家有用，-FPGA and the USB line of communication through the source code, nice and strong, we want to be useful, haha
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CY7c68013_fpga_write_sram\CY7c68013_fpga_write_sram\FPGA\bitgen.ut
.........................\.........................\....\coregen.prj
.........................\.........................\....\FPGA.dhp
.........................\.........................\....\FPGA.npl
.........................\.........................\....\prom.mcs
.........................\.........................\....\prom.prm
.........................\.........................\....\prom.sig
.........................\.........................\....\top(读flag另为一个状态).vhdl
.........................\.........................\....\top.bgn
.........................\.........................\....\top.bit
.........................\.........................\....\top.bld
.........................\.........................\....\top.cmd_log
.........................\.........................\....\top.drc
.........................\.........................\....\top.ll
.........................\.........................\....\top.lso
.........................\.........................\....\top.mrp
.........................\.........................\....\top.msd
.........................\.........................\....\top.msk
.........................\.........................\....\top.nc1
.........................\.........................\....\top.ncd
.........................\.........................\....\top.ngc
.........................\.........................\....\top.ngd
.........................\.........................\....\top.ngm
.........................\.........................\....\top.ngr
.........................\.........................\....\top.pad
.........................\.........................\....\top.pad_txt
.........................\.........................\....\top.par
.........................\.........................\....\top.pcf
.........................\.........................\....\top.placed_ncd_tracker
.........................\.........................\....\top.prj
.........................\.........................\....\top.rbb
.........................\.........................\....\top.rbd
.........................\.........................\....\top.routed_ncd_tracker
.........................\.........................\....\top.stx
.........................\.........................\....\top.syr
.........................\.........................\....\top.twr
.........................\.........................\....\top.twx
.........................\.........................\....\top.ut
.........................\.........................\....\top.vhdl
.........................\.........................\....\top.xpi
.........................\.........................\....\top_1.vhdl
.........................\.........................\....\top_2.vhdl
.........................\.........................\....\top_last_par.ncd
.........................\.........................\....\top_map.ncd
.........................\.........................\....\top_map.ngm
.........................\.........................\....\top_pad.csv
.........................\.........................\....\top_pad.txt
.........................\.........................\....\ucf.ucf
.........................\.........................\....\ucf.ucf.untf
.........................\.........................\....\xst\work\hdllib.ref
.........................\.........................\....\...\....\hdpdeps.ref
.........................\.........................\....\...\....\sub00\vhpl00.vho
.........................\.........................\....\...\....\.....\vhpl01.vho
.........................\.........................\....\_impact.cmd
.........................\.........................\....\.ngo\netlist.lst
.........................\.........................\....\._projnav\bitgen.rsp
.........................\.........................\....\.........\coregen.rsp
.........................\.........................\....\.........\ednTOngd_tcl.rsp
.........................\.........................\....\.........\FPGA.gfl
.........................
.........................\.........................\....\coregen.prj
.........................\.........................\....\FPGA.dhp
.........................\.........................\....\FPGA.npl
.........................\.........................\....\prom.mcs
.........................\.........................\....\prom.prm
.........................\.........................\....\prom.sig
.........................\.........................\....\top(读flag另为一个状态).vhdl
.........................\.........................\....\top.bgn
.........................\.........................\....\top.bit
.........................\.........................\....\top.bld
.........................\.........................\....\top.cmd_log
.........................\.........................\....\top.drc
.........................\.........................\....\top.ll
.........................\.........................\....\top.lso
.........................\.........................\....\top.mrp
.........................\.........................\....\top.msd
.........................\.........................\....\top.msk
.........................\.........................\....\top.nc1
.........................\.........................\....\top.ncd
.........................\.........................\....\top.ngc
.........................\.........................\....\top.ngd
.........................\.........................\....\top.ngm
.........................\.........................\....\top.ngr
.........................\.........................\....\top.pad
.........................\.........................\....\top.pad_txt
.........................\.........................\....\top.par
.........................\.........................\....\top.pcf
.........................\.........................\....\top.placed_ncd_tracker
.........................\.........................\....\top.prj
.........................\.........................\....\top.rbb
.........................\.........................\....\top.rbd
.........................\.........................\....\top.routed_ncd_tracker
.........................\.........................\....\top.stx
.........................\.........................\....\top.syr
.........................\.........................\....\top.twr
.........................\.........................\....\top.twx
.........................\.........................\....\top.ut
.........................\.........................\....\top.vhdl
.........................\.........................\....\top.xpi
.........................\.........................\....\top_1.vhdl
.........................\.........................\....\top_2.vhdl
.........................\.........................\....\top_last_par.ncd
.........................\.........................\....\top_map.ncd
.........................\.........................\....\top_map.ngm
.........................\.........................\....\top_pad.csv
.........................\.........................\....\top_pad.txt
.........................\.........................\....\ucf.ucf
.........................\.........................\....\ucf.ucf.untf
.........................\.........................\....\xst\work\hdllib.ref
.........................\.........................\....\...\....\hdpdeps.ref
.........................\.........................\....\...\....\sub00\vhpl00.vho
.........................\.........................\....\...\....\.....\vhpl01.vho
.........................\.........................\....\_impact.cmd
.........................\.........................\....\.ngo\netlist.lst
.........................\.........................\....\._projnav\bitgen.rsp
.........................\.........................\....\.........\coregen.rsp
.........................\.........................\....\.........\ednTOngd_tcl.rsp
.........................\.........................\....\.........\FPGA.gfl
.........................