文件名称:serial
介绍说明－－下载内容均来自于网络，请自行研究使用
用FPGA实现带有使能的串行数据的发送，并要求逻辑上可以自动停止，启动。-Achieved with the use of FPGA enables the serial data sent, and called logic can automatically stop, start.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
串行数据发送\db\ini.asm.qmsg
............\..\ini.asm_labs.ddb
............\..\ini.cbx.xml
............\..\ini.cmp.cdb
............\..\ini.cmp.hdb
............\..\ini.cmp.kpt
............\..\ini.cmp.logdb
............\..\ini.cmp.rdb
............\..\ini.cmp.tdb
............\..\ini.cmp0.ddb
............\..\ini.dbp
............\..\ini.db_info
............\..\ini.eco.cdb
............\..\ini.eda.qmsg
............\..\ini.eds_overflow
............\..\ini.fit.qmsg
............\..\ini.hier_info
............\..\ini.hif
............\..\ini.map.cdb
............\..\ini.map.hdb
............\..\ini.map.logdb
............\..\ini.map.qmsg
............\..\ini.pre_map.cdb
............\..\ini.pre_map.hdb
............\..\ini.psp
............\..\ini.rtlv.hdb
............\..\ini.rtlv_sg.cdb
............\..\ini.rtlv_sg_swap.cdb
............\..\ini.sgdiff.cdb
............\..\ini.sgdiff.hdb
............\..\ini.signalprobe.cdb
............\..\ini.sim.hdb
............\..\ini.sim.qmsg
............\..\ini.sim.rdb
............\..\ini.sim.vwf
............\..\ini.sld_design_entry.sci
............\..\ini.sld_design_entry_dsc.sci
............\..\ini.syn_hier_info
............\..\ini.tan.qmsg
............\..\wed.zsf
............\ini.asm.rpt
............\ini.done
............\ini.eda.rpt
............\ini.fit.rpt
............\ini.fit.smsg
............\ini.fit.summary
............\ini.flow.rpt
............\ini.map.rpt
............\ini.map.summary
............\ini.pin
............\ini.pof
............\ini.qpf
............\ini.qsf
............\ini.qws
............\ini.sim.rpt
............\ini.sof
............\ini.tan.rpt
............\ini.tan.summary
............\ini.v
............\ini.vwf
............\simulation\modelsim\ini.vo
............\..........\........\ini_modelsim.xrf
............\..........\........\ini_v.sdo
............\Verilog1.v
............\simulation\modelsim
............\db
............\simulation
串行数据发送
............\..\ini.asm_labs.ddb
............\..\ini.cbx.xml
............\..\ini.cmp.cdb
............\..\ini.cmp.hdb
............\..\ini.cmp.kpt
............\..\ini.cmp.logdb
............\..\ini.cmp.rdb
............\..\ini.cmp.tdb
............\..\ini.cmp0.ddb
............\..\ini.dbp
............\..\ini.db_info
............\..\ini.eco.cdb
............\..\ini.eda.qmsg
............\..\ini.eds_overflow
............\..\ini.fit.qmsg
............\..\ini.hier_info
............\..\ini.hif
............\..\ini.map.cdb
............\..\ini.map.hdb
............\..\ini.map.logdb
............\..\ini.map.qmsg
............\..\ini.pre_map.cdb
............\..\ini.pre_map.hdb
............\..\ini.psp
............\..\ini.rtlv.hdb
............\..\ini.rtlv_sg.cdb
............\..\ini.rtlv_sg_swap.cdb
............\..\ini.sgdiff.cdb
............\..\ini.sgdiff.hdb
............\..\ini.signalprobe.cdb
............\..\ini.sim.hdb
............\..\ini.sim.qmsg
............\..\ini.sim.rdb
............\..\ini.sim.vwf
............\..\ini.sld_design_entry.sci
............\..\ini.sld_design_entry_dsc.sci
............\..\ini.syn_hier_info
............\..\ini.tan.qmsg
............\..\wed.zsf
............\ini.asm.rpt
............\ini.done
............\ini.eda.rpt
............\ini.fit.rpt
............\ini.fit.smsg
............\ini.fit.summary
............\ini.flow.rpt
............\ini.map.rpt
............\ini.map.summary
............\ini.pin
............\ini.pof
............\ini.qpf
............\ini.qsf
............\ini.qws
............\ini.sim.rpt
............\ini.sof
............\ini.tan.rpt
............\ini.tan.summary
............\ini.v
............\ini.vwf
............\simulation\modelsim\ini.vo
............\..........\........\ini_modelsim.xrf
............\..........\........\ini_v.sdo
............\Verilog1.v
............\simulation\modelsim
............\db
............\simulation
串行数据发送