文件名称:fenpin
介绍说明--下载内容均来自于网络,请自行研究使用
在modelsim环境下实现的计数器分频,希望和大家分享-Realized in the environment in modelsim frequency counter, would like to share
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test3\work\_info
.....\....\.temp\vlogkv43t2
.....\....\.....\vlogixe61j
.....\....\.....\vloga3ta10
.....\....\.....\vlogz842c0
.....\....\.....\vlogza46f0
.....\....\.....\vlogztz6z1
.....\....\_vmake
.....\....\fdivision\_primary.vhd
.....\....\.........\_primary.dbs
.....\....\.........\_primary.dat
.....\....\.........\verilog.asm
.....\....\.........\verilog.rw
.....\....\division_@top\_primary.vhd
.....\....\.............\_primary.dbs
.....\....\.............\_primary.dat
.....\....\.............\verilog.asm
.....\....\.............\verilog.rw
.....\fdivision.v
.....\fdivision_Top.v
.....\fdivision.v.bak
.....\fdivision_Top.v.bak
.....\vsim.wlf
.....\fdivision.mpf
.....\fdivision.cr.mti
.....\work\_temp
.....\....\fdivision
.....\....\division_@top
.....\work
test3
.....\....\.temp\vlogkv43t2
.....\....\.....\vlogixe61j
.....\....\.....\vloga3ta10
.....\....\.....\vlogz842c0
.....\....\.....\vlogza46f0
.....\....\.....\vlogztz6z1
.....\....\_vmake
.....\....\fdivision\_primary.vhd
.....\....\.........\_primary.dbs
.....\....\.........\_primary.dat
.....\....\.........\verilog.asm
.....\....\.........\verilog.rw
.....\....\division_@top\_primary.vhd
.....\....\.............\_primary.dbs
.....\....\.............\_primary.dat
.....\....\.............\verilog.asm
.....\....\.............\verilog.rw
.....\fdivision.v
.....\fdivision_Top.v
.....\fdivision.v.bak
.....\fdivision_Top.v.bak
.....\vsim.wlf
.....\fdivision.mpf
.....\fdivision.cr.mti
.....\work\_temp
.....\....\fdivision
.....\....\division_@top
.....\work
test3