文件名称:uart16750

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [Linux] [Perl] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 148kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • max****
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

UART 16750 source code for VHDL
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart16750\branches

.........\tags\Import\bench\vhdl\slib_testbench.vhd

.........\....\......\.....\....\txt_util.vhd

.........\....\......\.....\....\uart_package.vhd

.........\....\......\.....\....\uart_transactor.vhd

.........\....\......\.....\vhdl

.........\....\......\bench

.........\....\......\doc\.README.swp

.........\....\......\...\LICENSE

.........\....\......\...\README

.........\....\......\doc

.........\....\......\rtl\vhdl\slib_clock_div.vhd

.........\....\......\...\....\slib_counter.vhd

.........\....\......\...\....\slib_edge_detect.vhd

.........\....\......\...\....\slib_fifo.vhd

.........\....\......\...\....\slib_fifo_cyclone2.vhd

.........\....\......\...\....\slib_input_filter.vhd

.........\....\......\...\....\slib_input_sync.vhd

.........\....\......\...\....\slib_mv_filter.vhd

.........\....\......\...\....\uart_16750.vhd

.........\....\......\...\....\uart_baudgen.vhd

.........\....\......\...\....\uart_interrupt.vhd

.........\....\......\...\....\uart_receiver.vhd

.........\....\......\...\....\uart_transmitter.vhd

.........\....\......\...\vhdl

.........\....\......\rtl

.........\....\......\sim\rtl_sim\bin\uart_test_stim.pl

.........\....\......\...\.......\bin

.........\....\......\...\.......\log\uart_log.txt

.........\....\......\...\.......\log

.........\....\......\...\.......\run\start_simulation.do

.........\....\......\...\.......\...\tb_uart_wave.do

.........\....\......\...\.......\run

.........\....\......\...\.......\src\uart_stim.dat

.........\....\......\...\.......\src

.........\....\......\...\rtl_sim

.........\....\......\sim

.........\....\Import

.........\tags

.........\.runk\bench\vhdl\slib_testbench.vhd

.........\.....\.....\....\txt_util.vhd

.........\.....\.....\....\uart_package.vhd

.........\.....\.....\....\uart_transactor.vhd

.........\.....\.....\vhdl

.........\.....\bench

.........\.....\doc\LICENSE

.........\.....\...\README

.........\.....\doc

.........\.....\rtl\vhdl\slib_clock_div.vhd

.........\.....\...\....\slib_counter.vhd

.........\.....\...\....\slib_edge_detect.vhd

.........\.....\...\....\slib_fifo.vhd

.........\.....\...\....\slib_fifo_cyclone2.vhd

.........\.....\...\....\slib_input_filter.vhd

.........\.....\...\....\slib_input_sync.vhd

.........\.....\...\....\slib_mv_filter.vhd

.........\.....\...\....\uart_16750.vhd

.........\.....\...\....\uart_baudgen.vhd

.........\.....\...\....\uart_interrupt.vhd

.........\.....\...\....\uart_receiver.vhd

.........\.....\...\....\uart_transmitter.vhd

.........\.....\...\vhdl

.........\.....\rtl

.........\.....\sim\rtl_sim\bin\uart_test_stim.pl

.........\.....\...\.......\bin

.........\.....\...\.......\log\uart_log.txt

.........\.....\...\.......\log

.........\.....\...\.......\run\Makefile

.........\.....\...\.......\...\start_simulation.do

.........\.....\...\.......\...\tb_uart_wave.do

.........\.....\...\.......\run

.........\.....\...\.......\src

.........\.....\...\rtl_sim

.........\.....\sim

.........\.....\.yn\Altera\CycloneII\slib_clock_div.bsf

.........\.....\...\......\.........\UART16750.asm.rpt

.........\.....\...\......\.........\UART16750.bdf

.........\.....\...\......\.........\UART16750.done

.........\.....\...\......\.........\UART16750.dpf

.........\.....\...\......\.........\UART16750.drc.rpt

.........\.....\...\......\.........\UART16750.fit.rpt

.........\.....\...\......\.........\UART16750.fit.smsg

.........\.....\...\......\.........\UART16750.fit.summary

.........\.....\...\......\.........\UART16750.flow.rpt

.........\.....\...\......\.........\UART16750.map.rpt

.........\.....\...\......\.........\UART16750.map.smsg

.........\.....\...\......\.........\UART16750.map.summary

.........\.....\...\......\.........\UART16750.qpf

.........\.....\...\......\.........\UART16750.qsf

.........\.....\...\......\.........\UART16750.qws

.........\.....\...\......\.........\UART16750.sdc

.........\.....\...\......\.........\UART16750.srf

.........\.....\...\......\.........\UART16750.tan.rpt

.........\.....\...\......\.........\UART16750.tan.summary

.........\.....\...\......\.........\uart_1675

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