文件名称:an501_design_example
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在MAX2系列CPLD上实现脉冲宽度调制(PWM),完整的设计成程序和仿真结果。-In the MAX2 series CPLD to realize pulse width modulation (PWM), a complete design and simulation results into the program.
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下载文件列表
an501_design_example\AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v
....................\.............................................................\modelsim\pulse_width_modulator.cr.mti
....................\.............................................................\........\pulse_width_modulator.mpf
....................\.............................................................\........\pwm_main.v
....................\.............................................................\........\pwm_sim.cr.mti
....................\.............................................................\........\pwm_sim.mpf
....................\.............................................................\........\test_pwm.v
....................\.............................................................\........\wave.bmp
....................\.............................................................\........\wave.do
....................\.............................................................\........\wave2.bmp
....................\.............................................................\........\wave2.do
....................\.............................................................\........\wave3.bmp
....................\.............................................................\........\wave3.do
....................\.............................................................\........\wave4.bmp
....................\.............................................................\........\wave4.do
....................\.............................................................\........\wave5.bmp
....................\.............................................................\........\wave5.do
....................\.............................................................\........\.ork\altufm_osc0_altufm_osc_1p3\verilog.asm
....................\.............................................................\........\....\..........................\_primary.dat
....................\.............................................................\........\....\..........................\_primary.vhd
....................\.............................................................\........\....\clkgen\verilog.asm
....................\.............................................................\........\....\......\_primary.dat
....................\.............................................................\........\....\......\_primary.vhd
....................\.............................................................\........\....\..._gen\verilog.asm
....................\.............................................................\........\....\.......\_primary.dat
....................\.............................................................\........\....\.......\_primary.vhd
....................\.............................................................\........\....\dutycycle\verilog.asm
....................\.............................................................\........\....\.........\_primary.dat
....................\.............................................................\........\....\.........\_primary.vhd
....................\.............................................................\........\....\...._cycle\verilog.asm
....................\.............................................................\........\....\..........\_primary.dat
....................\.............................................................\........\....\..........\_primary.vhd
....................\.............................................................\........\....\pwm_gen\verilog.asm
....................\.............................................................\........\....\.......\_primary.dat
....................\.............................................................\........\....\.......\_primary.vhd
....................\.............................................................\........\....\....main\verilog.asm
....................\..
....................\.............................................................\modelsim\pulse_width_modulator.cr.mti
....................\.............................................................\........\pulse_width_modulator.mpf
....................\.............................................................\........\pwm_main.v
....................\.............................................................\........\pwm_sim.cr.mti
....................\.............................................................\........\pwm_sim.mpf
....................\.............................................................\........\test_pwm.v
....................\.............................................................\........\wave.bmp
....................\.............................................................\........\wave.do
....................\.............................................................\........\wave2.bmp
....................\.............................................................\........\wave2.do
....................\.............................................................\........\wave3.bmp
....................\.............................................................\........\wave3.do
....................\.............................................................\........\wave4.bmp
....................\.............................................................\........\wave4.do
....................\.............................................................\........\wave5.bmp
....................\.............................................................\........\wave5.do
....................\.............................................................\........\.ork\altufm_osc0_altufm_osc_1p3\verilog.asm
....................\.............................................................\........\....\..........................\_primary.dat
....................\.............................................................\........\....\..........................\_primary.vhd
....................\.............................................................\........\....\clkgen\verilog.asm
....................\.............................................................\........\....\......\_primary.dat
....................\.............................................................\........\....\......\_primary.vhd
....................\.............................................................\........\....\..._gen\verilog.asm
....................\.............................................................\........\....\.......\_primary.dat
....................\.............................................................\........\....\.......\_primary.vhd
....................\.............................................................\........\....\dutycycle\verilog.asm
....................\.............................................................\........\....\.........\_primary.dat
....................\.............................................................\........\....\.........\_primary.vhd
....................\.............................................................\........\....\...._cycle\verilog.asm
....................\.............................................................\........\....\..........\_primary.dat
....................\.............................................................\........\....\..........\_primary.vhd
....................\.............................................................\........\....\pwm_gen\verilog.asm
....................\.............................................................\........\....\.......\_primary.dat
....................\.............................................................\........\....\.......\_primary.vhd
....................\.............................................................\........\....\....main\verilog.asm
....................\..