文件名称:ADSP_2126x_HRM
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High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital applications interface (DAI), and JTAG
-High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital applications interface (DAI), and JTAG
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital applications interface (DAI), and JTAG
-High performance 32-bit/40-bit floating-point processor
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Single-instruction multiple-data (SIMD) computational architecture—
two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI® port, six serial
ports, a digital applications interface (DAI), and JTAG
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ADSP_2126x_HRM.pdf