文件名称:DC_ASSIGN

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 39kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • n*
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counter clock vhdl file for useful to dc compilier
相关搜索: vhdl
assign

(系统自动生成,下载前可以参看下载内容)

下载文件列表

DC_ASSIGN\DC_TUT\top_down\READ_ME.txt

.........\......\........\src\vhdl\ALARM_BLOCK.vhd

.........\......\........\...\....\ALARM_COUNTER.vhd

.........\......\........\...\....\ALARM_SM_2.vhd

.........\......\........\...\....\ALARM_STATE_MACHINE.vhd

.........\......\........\...\....\clk_mul.vhd

.........\......\........\...\....\COMPARATOR.vhd

.........\......\........\...\....\CONVERTOR.pla

.........\......\........\...\....\CONVERTOR_CKT.vhd

.........\......\........\...\....\HOURS_FILTER.vhd

.........\......\........\...\....\MUX.vhd

.........\......\........\...\....\synopsys.vhd

.........\......\........\...\....\TIME_BLOCK.vhd

.........\......\........\...\....\TIME_COUNTER.vhd

.........\......\........\...\....\TIME_STATE_MACHINE.vhd

.........\......\........\...\....\TOP.vhd

.........\......\........\...\vhdl

.........\......\........\...\.erilog\ALARM_BLOCK.v

.........\......\........\...\.......\ALARM_COUNTER.v

.........\......\........\...\.......\ALARM_SM_2.v

.........\......\........\...\.......\ALARM_STATE_MACHINE.v

.........\......\........\...\.......\COMPARATOR.v

.........\......\........\...\.......\CONVERTOR.pla

.........\......\........\...\.......\CONVERTOR_CKT.v

.........\......\........\...\.......\HOURS_FILTER.v

.........\......\........\...\.......\MUX.v

.........\......\........\...\.......\TIME_BLOCK.v

.........\......\........\...\.......\TIME_COUNTER.v

.........\......\........\...\.......\TIME_STATE_MACHINE.v

.........\......\........\...\.......\TOP.v

.........\......\........\...\verilog

.........\......\........\src

.........\......\top_down

.........\......\bottom_up\src\vhdl\ALARM_BLOCK.vhd

.........\......\.........\...\....\ALARM_COUNTER.vhd

.........\......\.........\...\....\ALARM_SM_2.vhd

.........\......\.........\...\....\ALARM_STATE_MACHINE.vhd

.........\......\.........\...\....\COMPARATOR.vhd

.........\......\.........\...\....\CONVERTOR.pla

.........\......\.........\...\....\CONVERTOR_CKT.vhd

.........\......\.........\...\....\HOURS_FILTER.vhd

.........\......\.........\...\....\MUX.vhd

.........\......\.........\...\....\synopsys.vhd

.........\......\.........\...\....\TIME_BLOCK.vhd

.........\......\.........\...\....\TIME_COUNTER.vhd

.........\......\.........\...\....\TIME_STATE_MACHINE.vhd

.........\......\.........\...\....\TOP.vhd

.........\......\.........\...\vhdl

.........\......\.........\...\.erilog\ALARM_BLOCK.v

.........\......\.........\...\.......\ALARM_COUNTER.v

.........\......\.........\...\.......\ALARM_SM_2.v

.........\......\.........\...\.......\ALARM_STATE_MACHINE.v

.........\......\.........\...\.......\COMPARATOR.v

.........\......\.........\...\.......\CONVERTOR.pla

.........\......\.........\...\.......\CONVERTOR_CKT.v

.........\......\.........\...\.......\HOURS_FILTER.v

.........\......\.........\...\.......\MUX.v

.........\......\.........\...\.......\TIME_BLOCK.v

.........\......\.........\...\.......\TIME_COUNTER.v

.........\......\.........\...\.......\TIME_STATE_MACHINE.v

.........\......\.........\...\.......\TOP.v

.........\......\.........\...\verilog

.........\......\.........\src

.........\......\bottom_up

.........\DC_TUT

.........\crc\src\verilog\ht_phy.v

.........\...\...\.......\ht_phy_crc.v

.........\...\...\.......\rx_core.v

.........\...\...\verilog

.........\...\src

.........\crc

.........\Counter_clock_divider\src\clock_divider.vhd

.........\.....................\...\counter_led.vhd

.........\.....................\...\top_module.vhd

.........\.....................\src

.........\Counter_clock_divider

DC_ASSIGN

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