文件名称:uart1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 232kb
  • 下载次数:
  • 0次
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  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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RS232(UART)串口传输,通过了FPGA验证功能正确-UART RS232 verilog HDL

FPGA xilinx
(系统自动生成,下载前可以参看下载内容)

下载文件列表

uart\clkdiv.v

....\device_usage_statistics.html

....\smartpreview.twr

....\testuart.v

....\uart.bgn

....\uart.bit

....\uart.bld

....\uart.cmd_log

....\uart.drc

....\uart.gise

....\uart.ise

....\uart.lso

....\uart.ncd

....\uart.ngc

....\uart.ngd

....\uart.ngr

....\uart.ntrc_log

....\uart.pad

....\uart.par

....\uart.pcf

....\uart.prj

....\uart.ptwx

....\uart.stx

....\uart.syr

....\uart.twr

....\uart.twx

....\uart.ucf

....\uart.unroutes

....\uart.ut

....\uart.v

....\uart.xise

....\uart.xpi

....\uart.xst

....\uartrx.v

....\uarttx.v

....\uart_guide.ncd

....\uart_map.map

....\uart_map.mrp

....\uart_map.ncd

....\uart_map.ngm

....\uart_map.xrpt

....\uart_ngdbuild.xrpt

....\uart_pad.csv

....\uart_pad.txt

....\uart_par.xrpt

....\uart_prev_built.ngd

....\uart_summary.html

....\uart_summary.xml

....\uart_top_summary.html

....\uart_usage.xml

....\.....xdb\cst.xbcd

....\........\tmp\ise\version

....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject

....\........\...\...\............\..................\.........\HDProject_StrTbl

....\........\...\...\............\..................\__stored_object_table__

....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl

....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl

....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main

....\........\...\...\............\................\................\dpm_project_main_StrTbl

....\........\...\...\............\................Gui\CViewSelector

....\........\...\...\............\...................\CViewSelector_StrTbl

....\........\...\...\............\...................\File-SynthesisOnly

....\........\...\...\............\...................\File-SynthesisOnly_StrTbl

....\........\...\...\............\...................\Library-SynthesisOnly

....\........\...\...\............\...................\Library-SynthesisOnly_StrTbl

....\........\...\...\............\...................\Process-SynthesisOnly-

....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF

....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl

....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG

....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl

....\........\...\...\............\...................\Process-SynthesisOnly-_StrTbl

....\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile

....\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl

....\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module

....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl

....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-uart

....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-uart_StrTbl

....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-uart_top

....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-uart_top_StrTbl

....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default

....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl

....\........\...\...\..REGISTRY__\Autonym\regkeys

....\........\...\...\............\bitgen\regkeys

....\........\...\...\............\...init\regkeys

....\........\...\...\............\common\regkeys

....\........\...\...\............\.pldfit\regkeys

....\........\...\...\............\dumpngdio\regkeys

....\........\...\...\............\ExpandedNetlistEngine\regkeys

....\........\...\...\............\fuse\regkeys

....\........\...\...\............\HierarchicalDesign\HDProject\regkeys

....\........\...\...\............\..................\regkeys

....\........\...\...\............\hprep6\regkeys

....\........\...\...\............\idem\regkeys

....\........\...\...\............\libgen\regkeys

....\........\...\...\............\map\regkeys

....\........\...\...\............\netgen\regkeys

..

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