文件名称:verilog232

  • 所属分类:
  • 其他小程序
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 511kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 雪*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

该源码是关于Veriloghdl语言编写的rs232串口实现,通过下载得到验证-The source code is written in on the Veriloghdl rs232 serial interface, be verified by downloading
相关搜索: verilog232

(系统自动生成,下载前可以参看下载内容)

下载文件列表

serial_com\async_receiver.v

..........\async_receiver_summary.html

..........\async_transmitter.v

..........\device_usage_statistics.html

..........\netgen\par\serialfun_timesim.nlf

..........\......\...\serialfun_timesim.sdf

..........\......\...\serialfun_timesim.v

..........\serialfun.bgn

..........\serialfun.bit

..........\serialfun.bld

..........\serialfun.cel

..........\serialfun.cmd_log

..........\serialfun.drc

..........\serialfun.lfp

..........\serialfun.lso

..........\serialfun.ncd

..........\serialfun.ngc

..........\serialfun.ngd

..........\serialfun.ngr

..........\serialfun.pad

..........\serialfun.par

..........\serialfun.pcf

..........\serialfun.prj

..........\serialfun.stx

..........\serialfun.syr

..........\serialfun.twr

..........\serialfun.twx

..........\serialfun.ucf

..........\serialfun.unroutes

..........\serialfun.ut

..........\serialfun.v

..........\serialfun.xpi

..........\serialfun.xst

..........\serialfun_guide.ncd

..........\serialfun_map.map

..........\serialfun_map.mrp

..........\serialfun_map.ncd

..........\serialfun_map.ngm

..........\serialfun_pad.csv

..........\serialfun_pad.txt

..........\serialfun_prev_built.ngd

..........\serialfun_summary.html

..........\serialfun_summary.xml

..........\serialfun_usage.xml

..........\serial_com.ise

..........\serial_com.ise_ISE_Backup

..........\serial_com.ntrc_log

..........\serial_com.restore

..........\serial_test.ant

..........\serial_test.jhd

..........\serial_test.tbw

..........\serial_test.tdo

..........\serial_test.tfw

..........\serial_test.udo

..........\serial_test.xwv

..........\serial_test.xwv_bak

..........\serial_test_bencher.prj

..........\transcript

..........\vsim.wlf

..........\work\glbl\verilog.psm

..........\....\....\_primary.dat

..........\....\....\_primary.vhd

..........\....\serialfun\verilog.psm

..........\....\.........\_primary.dat

..........\....\.........\_primary.vhd

..........\....\......_test\verilog.psm

..........\....\...........\_primary.dat

..........\....\...........\_primary.vhd

..........\....\_info

..........\xst\dump.xst\serialfun.prj\ntrc.scr

..........\...\work\hdllib.ref

..........\...\....\vlg32\async__transmitter.bin

..........\...\....\....A\async__receiver.bin

..........\...\....\...4D\serialfun.bin

..........\_ngo\netlist.lst

..........\_pace.ucf

..........\.xmsgs\bitgen.xmsgs

..........\......\map.xmsgs

..........\......\netgen.xmsgs

..........\......\ngdbuild.xmsgs

..........\......\par.xmsgs

..........\......\trce.xmsgs

..........\......\xst.xmsgs

..........\__ISE_repository_serial_com.ise_.lock

..........\xst\dump.xst\serialfun.prj\ngx\notopt

..........\...\........\.............\...\opt

..........\...\........\.............\ngx

..........\...\........\serialfun.prj

..........\...\work\vlg32

..........\...\....\vlg3A

..........\...\....\vlg4D

..........\netgen\par

..........\work\glbl

..........\....\serialfun

..........\....\serial_test

..........\....\_temp

..........\xst\dump.xst

..........\...\projnav.tmp

..........\...\work

..........\netgen

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